Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46820 )
Change subject: cpu/x86: Use class for sipi module ......................................................................
cpu/x86: Use class for sipi module
This removes the hardcoded single assembly file and allows to add more source files to the SIPI rmodule.
This can be used to link C code for reusing existing code.
Change-Id: I701eb340688e43591dfca77f55106c5b2f1a7735 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Makefile.inc M src/cpu/x86/Makefile.inc 2 files changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46820/1
diff --git a/Makefile.inc b/Makefile.inc index bf33f8b..6b015f7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -93,7 +93,7 @@
####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock decompressor postcar smm smmstub cpu_microcode verstage +classes-y := ramstage romstage bootblock decompressor postcar sipi_vec smm smmstub cpu_microcode verstage
# Add a special 'all' class to add sources to all stages $(call add-special-class,all) diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 2f789f7..66b1a68 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -23,10 +23,14 @@ ifeq ($(CONFIG_PARALLEL_MP),y) $(TARGET_STAGE)-srcs += $(SIPI_BIN).manual endif -rmodules_$(ARCH-$(TARGET_STAGE)-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S
-$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-$(TARGET_STAGE)-y),src/cpu/x86/sipi_vector.S) - $(LD_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^ +$(eval $(call create_class_compiler,sipi_vec,$(ARCH-$(TARGET_STAGE)-y))) +sipi_vec-generic-ccopts = $(rmodule_$(ARCH-$(TARGET_STAGE)-y)-generic-ccopts) + +sipi_vec-$(CONFIG_PARALLEL_MP) += sipi_vector.S + +$(SIPI_DOTO): $$(sipi_vec-objs) $(COMPILER_RT_sipi_vec) + $(LD_sipi_vec) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_sipi_vec) --whole-archive --start-group $(sipi_vec-objs) --no-whole-archive $(COMPILER_RT_sipi_vec) --end-group
$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,$(ARCH-$(TARGET_STAGE)-y)))