[coreboot-gerrit] Change in coreboot[master]: sb/intel/nm10: Fix enabling HPET

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35758 )

Change subject: sb/intel/nm10: Fix enabling HPET
......................................................................

sb/intel/nm10: Fix enabling HPET

RCBA_HPTC needs to be read back to consistently enable HPET.
This ought to fix raminit failing sometimes and SeaBIOS endlessly
waiting for user input.

TESTED on Intel D510MO, Fixes SeaBIOS waiting for input, without a
timeout.

Change-Id: I20a25fd97cd09fedb70469262c64d8d3828bb684
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35758
Reviewed-by: Patrick Rudolph 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/pineview/raminit.c
M src/southbridge/intel/i82801gx/lpc.c
2 files changed, 8 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve
  Name of user not set #1002601: Looks good to me, but someone else must approve

diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 5cece41..7f59d91 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -552,10 +552,12 @@
 static void enable_hpet(void)
 {
    u32 reg32;
-	reg32 = RCBA32(0x3404);
+	reg32 = RCBA32(HPTC);
    reg32 &= ~0x3;
    reg32 |= (1 << 7);
-	RCBA32(0x3404) = reg32;
+	RCBA32(HPTC) = reg32;
+	/* On NM10 this only works if read back */
+	RCBA32(HPTC);
    HPET32(0x10) = HPET32(0x10) | 1;
 }

diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 4e2f9f9..62576c1 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -310,6 +310,10 @@
    reg32 |= (1 << 7); // HPET Address Enable
    reg32 &= ~(3 << 0);
    RCBA32(HPTC) = reg32;
+	/* On NM10 this only works if read back */
+	RCBA32(HPTC);
+
+	write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1);
 }

static void enable_clock_gating(void)