Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43839 )
Change subject: {sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits ......................................................................
{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits
We have definitions for the bits in the PCI COMMAND register. Use them.
Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/scc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/lpss.c M src/soc/intel/broadwell/sata.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/sata.c 18 files changed, 39 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43839/1
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 0da1fe4..0ee3cef 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -205,7 +205,7 @@
static const struct reg_script gpu_pre_vbios_script[] = { /* Make sure GFX is bus master with MMIO access */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY), /* Display */ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 08c3c05..afeb687 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -19,7 +19,8 @@ { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), + REG_PCI_OR16(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 0b7a8c6..7e6bcab 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -36,7 +36,7 @@ pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); /* Enable decode of I/O space. */ reg = pci_read_config16(smbus_dev, PCI_COMMAND); - reg |= 0x1; + reg |= PCI_COMMAND_IO; pci_write_config16(smbus_dev, PCI_COMMAND, reg); /* Enable Host Controller */ reg = pci_read_config8(smbus_dev, 0x40); diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index f178e83..3b19f1b 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -74,7 +74,7 @@ struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR16(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 1bd0033..7599329 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -14,7 +14,7 @@
static const struct reg_script gpu_pre_vbios_script[] = { /* Make sure GFX is bus master with MMIO access */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY), REG_SCRIPT_END };
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index 7ff42c3..961d405 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -19,7 +19,8 @@ { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), + REG_PCI_OR16(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index 5ddccc5..e7135f7 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -36,7 +36,8 @@ printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
/* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 2efddd8..2407d92 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -520,7 +520,9 @@ report_pch_info(dev);
/* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */ pch_enable_ioapic(dev); diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 63801a2..484f0f1 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -108,7 +108,8 @@ /* SATA configuration */
/* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* AHCI */ if (sata_mode == 0) { diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 3a71dbc..dec1266 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -253,7 +253,9 @@ static void lpc_init(struct device *dev) { /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
i82801dx_enable_acpi(dev); /* IO APIC initialization. */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9b32f6c..0c76781 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -347,7 +347,9 @@ printk(BIOS_DEBUG, "i82801gx: %s\n", __func__);
/* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */ i82801gx_enable_ioapic(dev); diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 6efdef7..715d670 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -88,7 +88,8 @@ ports = get_ich7_sata_ports();
/* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
switch (config->sata_mode) { case SATA_MODE_IDE_LEGACY_COMBINED: diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 883c964..e539003 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -357,7 +357,9 @@ printk(BIOS_DEBUG, "i82801ix: %s\n", __func__);
/* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */ i82801ix_enable_apic(dev); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 2533d8c..ebeb2ee 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -361,7 +361,9 @@ printk(BIOS_DEBUG, "i82801jx: %s\n", __func__);
/* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */ i82801jx_enable_apic(dev); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 7e99613..230d5eb 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -439,7 +439,9 @@ printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */ pch_enable_ioapic(dev); diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 357ad5f..2137149 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -49,7 +49,8 @@ /* SATA configuration */
/* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (sata_mode == 0) { /* AHCI */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f3298b0..7082a79 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -505,7 +505,9 @@ printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */ pch_enable_ioapic(dev); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 47e6f9b..2f903f0 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -41,7 +41,8 @@ /* SATA configuration */
/* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");