[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp/spr/acpi: Allow OS to control LTR

[Patrick Rudolph (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85561?usp=email )

Change subject: soc/intel/xeon_sp/spr/acpi: Allow OS to control LTR
......................................................................

soc/intel/xeon_sp/spr/acpi: Allow OS to control LTR

There's no reason to tell the OS to disable LTR. On UEFI and
on coreboot's GNR LTR is allowed, thus allow it for all Xeon-SP.

TEST: Run code on ocp/tiogapass and observed dmesg:
      The OS now prints:
acpi PNP0A08:04: _OSC: OS now controls [PME PCIeCapability LTR]

Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
3 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/85561/1

diff --git a/src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl b/src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl
index f8eb59e..c437056 100644
--- a/src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl
+++ b/src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl
@@ -30,7 +30,7 @@
    	Name (_PXM, pxm)  /* _PXM: Device Proximity */		\
    	Method (_OSC, 4, NotSerialized)				\
    	{							\
-			Return (_SB.POSC(Arg0, Arg1, Arg2, Arg3, 0x15, 0 , 0)) \
+			Return (_SB.POSC(Arg0, Arg1, Arg2, Arg3, 0x35, 0 , 0)) \
    	}							\
    }

diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
index 2d98277..7e8859c 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
@@ -38,6 +38,6 @@
    }
    Method (_OSC, 4, NotSerialized)
    {
-		Return (_SB.POSC(Arg0, Arg1, Arg2, Arg3, 0x15, 1, 1))
+		Return (_SB.POSC(Arg0, Arg1, Arg2, Arg3, 0x35, 1, 1))
    }
 }
diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
index 498f897..e56cbb5 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
@@ -36,6 +36,6 @@

Method (_OSC, 4, NotSerialized)
    {
-		Return (_SB.POSC(Arg0, Arg1, Arg2, Arg3, 0x15, 0, 0))
+		Return (_SB.POSC(Arg0, Arg1, Arg2, Arg3, 0x35, 0, 0))
    }
 }