Attention is currently required from: Nick Vaccaro, Karthik Ramasubramanian. Hello Nick Vaccaro, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60016
to look at the new patch set (#2).
Change subject: drivers/generic/bayhub_lv2: Add workaround for known errata ......................................................................
drivers/generic/bayhub_lv2: Add workaround for known errata
The Bayhub LV2 has a known errata wherein PCI config registers at offsets 0x234, 0x238, and 0x24C will only correctly accept writes when they are addressed via a DWORD (32-bit) wide write operation on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop latency register, therefore add a finalize callback to this driver which will program the LTR max-snoop/no-snoop register with a 32-bit write using the values from pciexp_get_ltr_max_latencies().
BUG=b:204343849 TEST=verified the PCI config space writes took effect on google/taeko
Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/drivers/generic/bayhub_lv2/lv2.c 1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/60016/2