[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/21459 )

Change subject: mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden
......................................................................

Patch Set 1:
> (1 comment)

Why we are not setting UPD as PCI mode and take advantage of below code as coreboot already initialize LPSS UART 2 device in PCI mode in bootblock

case PchSerialIoPci:
      //
      //  Check If device is already initialized
      //
      if (PciSegmentRead32 (PciCfgBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000) {
        return;
      }

Then it has to return rather doing further legacy programming if i use your CL that mean since BB till FSP-S entry we are in 32 bit mode and at exist we are in 8 bit mode again. Because if policy is 
   if (DeviceMode == PchSerialIoHidden) {
      Data32Or = (B_SERIAL_IO_PCR_GPPRVRW7_UART0_BYTE_ADDR_EN << (Controller - PchSerialIoIndexUart0));
    }
then only FSP will set into leagcy 16550 - 8bit mode.

If you still have confusion then raise HSD, i will try to clarify but i don't think this CL make sense