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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58114
to look at the new patch set (#5).
Change subject: soc/amd/common/block/espi_util: Refactor eSPI Setup ......................................................................
soc/amd/common/block/espi_util: Refactor eSPI Setup
eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled.
BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 --- M src/soc/amd/cezanne/bootblock.c M src/soc/amd/cezanne/early_fch.c M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c M src/soc/amd/picasso/early_fch.c 6 files changed, 19 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/58114/5