Attention is currently required from: Subrata Banik.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 )
Change subject: soc/intel/common/thermal: Allow thermal configuration over PMC
......................................................................
Patch Set 14:
(2 comments)
Patchset:
PS14:
I wonder how this could ever work on TGL, where TTSuggestedSetting is 1 by default, causing TT registers to be set and locked by fsp in PEI...
File src/soc/intel/common/block/thermal/thermal_pmc.c:
https://review.coreboot.org/c/coreboot/+/59209/comment/c15db1f7_bd0e673c
PS14, Line 78: {
: .offset = PMC_PWRM_THERMAL_PHLC,
: .value = PMC_PWRM_THERMAL_PHLC_PHLCLOCK,
: },
: {
: .offset = PMC_PWRM_THERMAL_TLEN,
: .value = PMC_PWRM_THERMAL_TLEN_TLENLOCK,
: },
set by FSP unconditionally
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