[coreboot-gerrit] [S] Change in coreboot[master]: [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device()

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74441 )

Change subject: [WIP] cpu/intel/speedstep: Use acpigen_write_processor_device()
......................................................................

[WIP] cpu/intel/speedstep: Use acpigen_write_processor_device()

TBD: In case of no _CST entries, add valid _PTC ?

Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/intel/speedstep/acpi.c
M src/southbridge/intel/i82801gx/fadt.c
M src/southbridge/intel/i82801ix/fadt.c
M src/southbridge/intel/i82801jx/fadt.c
4 files changed, 22 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/74441/1

diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 0a13445..b27e29d 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -72,8 +72,6 @@

static void generate_cpu_entry(int cpu, int core, int cores_per_package)
 {
-	int pcontrol_blk = PMB0_BASE, plen = 6;
-
    static struct {
    	int once;
    	uint8_t coordination;
@@ -89,13 +87,8 @@
    	speedstep_gen_pstates(&s.pstates);
    }

-	if (core > 0) {
-		pcontrol_blk = 0;
-		plen = 0;
-	}
-
-	/* Generate processor _SB.CPUx. */
-	acpigen_write_processor(cpu * cores_per_package + core, pcontrol_blk, plen);
+	/* Generate Scope(_SB) { Device(CPUx */
+	acpigen_write_processor_device(cpu * cores_per_package + core);

/* Generate p-state entries. */
    gen_pstate_entries(&s.pstates, cpu, cores_per_package, s.coordination);
@@ -104,7 +97,7 @@
    if (s.num_cstates > 0)
    	acpigen_write_CST_package(s.cstates, s.num_cstates);

-	acpigen_pop_len();
+	acpigen_write_processor_device_end();
 }

/**
diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c
index 6d63e72..ae9a77f 100644
--- a/src/southbridge/intel/i82801gx/fadt.c
+++ b/src/southbridge/intel/i82801gx/fadt.c
@@ -34,6 +34,7 @@
    fadt->pm2_cnt_len = 1;
    fadt->pm_tmr_len = 4;
    fadt->gpe0_blk_len = 8;
+
    fadt->p_lvl2_lat = 1;
    fadt->p_lvl3_lat = chip->c3_latency;
    fadt->duty_offset = 1;
@@ -41,6 +42,7 @@
    	fadt->duty_width = 3;
    else
    	fadt->duty_width = 0;
+
    fadt->day_alrm = 0xd;
    fadt->mon_alrm = 0x00;
    fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES;
diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c
index 54ebcbd..5bceffe 100644
--- a/src/southbridge/intel/i82801ix/fadt.c
+++ b/src/southbridge/intel/i82801ix/fadt.c
@@ -30,10 +30,12 @@
    fadt->pm2_cnt_len = 1;
    fadt->pm_tmr_len = 4;
    fadt->gpe0_blk_len = 16;
+
    fadt->p_lvl2_lat = 1;
    fadt->p_lvl3_lat = 0x39;
    fadt->duty_offset = 1;
    fadt->duty_width = 3;
+
    fadt->day_alrm = 0xd;
    fadt->mon_alrm = 0x00;
    fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index 9d60ca5a..aa60aaf 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -30,10 +30,13 @@
    fadt->pm2_cnt_len = 1;
    fadt->pm_tmr_len = 4;
    fadt->gpe0_blk_len = 16;
+
    fadt->p_lvl2_lat = 1;
    fadt->p_lvl3_lat = 0;	/* FIXME: Is this correct? */
+
    fadt->duty_offset = 1;
    fadt->duty_width = 0;
+
    fadt->day_alrm = 0xd;
    fadt->mon_alrm = 0x00;
    fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES;