John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41762 )
Change subject: soc/intel/tigerlake: Add Type-C IOM device ......................................................................
soc/intel/tigerlake: Add Type-C IOM device
This adds Type-C IO Manageability Engine device with HID INTC1072. It provides MMIO range from 0xfbc10000 with size 0x1600. Kernel IOM driver refers to this memory resource for port operations.
BUG=:b:156016218 TEST=Built and booted on Volteer.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ic733e831643bda6e052edf797ba0e6206eb4ddd3 --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41762/1
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index abdcb51..6ae5582 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -130,6 +130,18 @@
Scope (_SB.PCI0) { + Device (IOM) + { + Name (_HID, "INTC1072") + Name (_DDN, "Intel(R) Tiger Lake IO Manageability Engine") + /* + * IOM preserved MMIO range from 0xFBC10000 to 0xFBC11600. + */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) + }) + } + /* * Operation region defined to access the IOM REGBAR. Get the MCHBAR in offset * 0x48 in B0:D0:F0. REGBAR Base address is in offset 0x7110 of MCHBAR.