[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Saurabh Mishra (Code Review)]

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Saurabh Mishra.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................

Patch Set 75:

(1 comment)

File src/soc/intel/pantherlake/soundwire.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/27bb48d6_2bc3c7e6?usp... :
PS71, Line 38: 0x40000000,
> can we use a macro ? […]

Hi, as per comment from https://github.com/coreboot/coreboot/blob/main/src/drivers/intel/soundwire/s..., it says that , "not compatible with either PCI or SoundWire"

````
@acpi_address: ACPI address for this controller.  This is a custom address that is not
 *                compatible with either PCI or SoundWire.
````