[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Paul Menzel, Sowmya Aralguppe, Wonkyu Kim.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email )

Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
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Patch Set 13:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/83946/comment/fc0db73b_c39f4be9?usp... :
PS13, Line 28: 3
> The issue addressed by this commit can be observed with the following experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to 0x400000 (4 MB).

can you please let me know the per port cache size for LLC. Looking at MTL, I could confirm that per port cache is 3MB, therefore, DCACHE_RAM_SIZE set to 4MB is not practical.