Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13662
-gerrit
commit 7045dbe04bf4476eaa0fdc7b05a1c33c1cb62bc6 Author: Vladimir Serbinenko phcoder@gmail.com Date: Wed Feb 10 02:52:42 2016 +0100
stumpy: Add native raminit support
Change-Id: Ibbb056ae209a16533757af925c8c833c94803834 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/mainboard/samsung/stumpy/Kconfig | 4 ---- src/mainboard/samsung/stumpy/devicetree.cb | 2 ++ src/mainboard/samsung/stumpy/romstage.c | 25 +++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 50b1625..874dd6c 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -18,10 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MRC select INTEL_INT15
-config USE_NATIVE_RAMINIT - bool - default n - config CHROMEOS select PHYSICAL_REC_SWITCH select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index df91a72..901711b 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
+ register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 87528af..ab1cb76 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -31,6 +31,7 @@ #include <superio/ite/it8772f/it8772f.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> @@ -203,6 +204,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; }
+void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 1, 1, 0 }, /* P0: Front port (OC0) */ + { 1, 0, 1 }, /* P1: Back port (OC1) */ + { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, -1 }, /* P3: MMC (no OC) */ + { 1, 1, 2 }, /* P4: Front port (OC2) */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, 4 }, /* P8: Back port (OC4) */ + { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 1, 0, 6 }, /* P12: Back port (OC6) */ + { 1, 0, 5 }, /* P13: Back port (OC5) */ +}; + void mainboard_early_init(int s3resume) { init_bootmode_straps();