Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62296 )
Change subject: mb/google/brya: enable the SPD_CACHE_ENABLE ......................................................................
mb/google/brya: enable the SPD_CACHE_ENABLE
google/brask is using SODIMMs for DRAM. Reading spd data is surprisingly slow (~170 ms), therefore enable the SPD cache.
BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=run on the device and measure the boot time decrease.
Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db Signed-off-by: Zhuohao Lee zhuohao@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/62296 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index f7bd715..00e8bc9 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -239,6 +239,7 @@
config MEMORY_SODIMM def_bool n + select SPD_CACHE_ENABLE select SPD_CACHE_IN_FMAP
config MEMORY_SOLDERDOWN