Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4176
-gerrit
commit e380962d337ca5e3f2689b48a5050dfab04c644a Author: Duncan Laurie dlaurie@chromium.org Date: Tue May 21 08:05:39 2013 -0700
slippy: Update interrupt routing
The SerialIO devices have specific requirements for PCI interrupt mode to use PIRQ{E,F,G,H} that are not being met.
D21:F0 uses PIRQE, which must not be shared with other PCH D21:F1-F6 share PIRQF, which must not be shared with other PCH D23:F0 uses PIRQH, which must not be shared with other PCH
- Fix D20IR -> D20IP typo - Remove D25/EHCI2 as it does not exist - Reorder other interrupts to clear PIRQE/PIRQF/PIRQH
Check device interrupts in the kernel
0: IO-APIC-edge timer 1: IO-APIC-edge i8042 8: IO-APIC-edge rtc0 9: IO-APIC-fasteoi acpi 16: IO-APIC-fasteoi ath9k 18: IO-APIC-fasteoi i801_smbus 19: IO-APIC-fasteoi ehci_hcd:usb1 21: IO-APIC-fasteoi i2c-designware-pci--1, i2c-designware-pci--1 40: PCI-MSI-edge PCIe PME 41: PCI-MSI-edge i915 42: PCI-MSI-edge ahci 43: PCI-MSI-edge xhci_hcd 44: PCI-MSI-edge snd_hda_intel
Change-Id: Id4c08d11d2860f270c6387138acdc7d3d83a85b5 Signed-off-by: Duncan Laurie dlaurie@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/56028 Reviewed-by: Aaron Durbin adurbin@chromium.org --- .../google/slippy/acpi/haswell_pci_irqs.asl | 51 ++++++++++++---------- src/mainboard/google/slippy/romstage.c | 30 ++++++------- 2 files changed, 42 insertions(+), 39 deletions(-)
diff --git a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl index a8b6b5f..82a2eba 100644 --- a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl +++ b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl @@ -29,26 +29,26 @@ Method(_PRT) // High Definition Audio 0:1b.0 Package() { 0x001bffff, 0, 0, 22 }, // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 18 }, - Package() { 0x001cffff, 2, 0, 19 }, - Package() { 0x001cffff, 3, 0, 20 }, + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, // EHCI 0:1d.0 Package() { 0x001dffff, 0, 0, 19 }, // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 16 }, + Package() { 0x0014ffff, 0, 0, 18 }, // LPC devices 0:1f.0 Package() { 0x001fffff, 0, 0, 21 }, - Package() { 0x001fffff, 1, 0, 22 }, - Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 17 }, Package() { 0x001fffff, 3, 0, 16 }, // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 16 }, - Package() { 0x0015ffff, 1, 0, 17 }, - Package() { 0x0015ffff, 2, 0, 18 }, - Package() { 0x0015ffff, 3, 0, 19 }, + Package() { 0x0015ffff, 0, 0, 20 }, + Package() { 0x0015ffff, 1, 0, 21 }, + Package() { 0x0015ffff, 2, 0, 21 }, + Package() { 0x0015ffff, 3, 0, 21 }, // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 16 }, + Package() { 0x0017ffff, 0, 0, 23 }, }) } Else { Return (Package() { @@ -57,19 +57,26 @@ Method(_PRT) // High Definition Audio 0:1b.0 Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKG, 0 }, // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKE, 0 }, - // EHCI #1 0:1d.0 + Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, + // EHCI 0:1d.0 Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, _SB.PCI0.LPCB.LNKE, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, _SB.PCI0.LPCB.LNKC, 0 }, // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001fffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, _SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0015ffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 2, _SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 3, _SB.PCI0.LPCB.LNKF, 0 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, }) } } diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index a02a84d..01f613d 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -35,13 +35,12 @@ const struct rcba_config_instruction rcba_config[] = {
/* * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQA + * D28IP_P1IP PCIE INTA -> PIRQA + * D29IP_E1P EHCI INTA -> PIRQD + * D20IP_XHCI XHCI INTA -> PIRQC (MSI) * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA * D27IP_ZIP HDA INTA -> PIRQG (MSI) */
@@ -53,21 +52,18 @@ const struct rcba_config_instruction rcba_config[] = { (INTB << D28IP_P4IP)), RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IR, (INTA << D20IP_XHCI)), + RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
/* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), - RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQA, 0, 0, 0)), + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ + RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ + RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ + RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
/* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),