Sorin Pop has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69493 )
Change subject: packeteer 6500 ......................................................................
packeteer 6500
Change-Id: Ie36fe8a4e0eaf13418af5a1fe8bd5b63f2265096 --- M src/arch/x86/pirq_routing.c M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc A src/cpu/intel/socket_FC_PGA370/Kconfig A src/cpu/intel/socket_FC_PGA370/Makefile.inc A src/cpu/intel/socket_FC_PGA370/socket_fc_pga370.c A src/mainboard/packeteer/6500/Kconfig A src/mainboard/packeteer/6500/Kconfig.name A src/mainboard/packeteer/6500/Makefile.inc A src/mainboard/packeteer/6500/acpi_tables.c A src/mainboard/packeteer/6500/bootblock.c A src/mainboard/packeteer/6500/devicetree.cb A src/mainboard/packeteer/6500/dsdt.asl A src/mainboard/packeteer/6500/dsdt.asl2 A src/mainboard/packeteer/6500/irq_tables.c A src/mainboard/packeteer/6500/irq_tables.c_ok A src/mainboard/packeteer/6500/mainboard.c A src/mainboard/packeteer/6500/superio.asl A src/mainboard/packeteer/Kconfig A src/mainboard/packeteer/Kconfig.name M src/southbridge/intel/i82371eb/acpi/i82371eb.asl M src/southbridge/intel/i82371eb/acpi/intx.asl M src/southbridge/intel/i82371eb/isa.c 23 files changed, 1,396 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/69493/1
diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 362650d..539c826 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -140,6 +140,10 @@ printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ", 'A' + intx, link, bitmap);
+ if (link > 0x5f) { + link -= 0x5f; + } + if (!bitmap || !link || link > CONFIG_MAX_PIRQ_LINKS) {
printk(BIOS_DEBUG, "not routed\n"); diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 43b360b..3414773 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -16,6 +16,7 @@ source "src/cpu/intel/haswell/Kconfig" # Sockets/Slots source "src/cpu/intel/slot_1/Kconfig" +source "src/cpu/intel/socket_FC_PGA370/Kconfig" source "src/cpu/intel/socket_BGA956/Kconfig" source "src/cpu/intel/socket_FCBGA559/Kconfig" source "src/cpu/intel/socket_m/Kconfig" diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 01913de..82da95d 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -14,6 +14,7 @@ subdirs-$(CONFIG_CPU_INTEL_MODEL_206AX) += model_206ax subdirs-$(CONFIG_CPU_INTEL_HASWELL) += haswell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
subdirs-y += common diff --git a/src/cpu/intel/socket_FC_PGA370/Kconfig b/src/cpu/intel/socket_FC_PGA370/Kconfig new file mode 100644 index 0000000..c2b1714 --- /dev/null +++ b/src/cpu/intel/socket_FC_PGA370/Kconfig @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Joseph Smith joe@settoplinux.org +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config CPU_INTEL_SOCKET_FC_PGA370 + bool + +if CPU_INTEL_SOCKET_FC_PGA370 + +config SLOT_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_MODEL_68X + select CPU_INTEL_MODEL_6BX + select CPU_INTEL_MODEL_6XX + select MMX + select SSE + select NO_SMM + select UDELAY_TSC + select TSC_MONOTONIC_TIMER + select UNKNOWN_TSC_RATE + select SETUP_XIP_CACHE +# select RESERVE_MTRRS_FOR_OS + +config DCACHE_RAM_BASE + hex + default 0xfefc0000 +# default 0xc8000 + +config DCACHE_RAM_SIZE + hex + default 0x08000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x1000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x10000 + + +endif diff --git a/src/cpu/intel/socket_FC_PGA370/Makefile.inc b/src/cpu/intel/socket_FC_PGA370/Makefile.inc new file mode 100644 index 0000000..945f0d6 --- /dev/null +++ b/src/cpu/intel/socket_FC_PGA370/Makefile.inc @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Joseph Smith joe@settoplinux.org +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += socket_fc_pga370.c + +subdirs-y += ../model_68x +subdirs-y += ../model_6xx +subdirs-y += ../model_6bx +subdirs-y += ../microcode + +bootblock-y += ../car/p3/cache_as_ram.S +bootblock-y += ../car/bootblock.c +postcar-y += ../car/p4-netburst/exit_car.S +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_FC_PGA370/socket_fc_pga370.c b/src/cpu/intel/socket_FC_PGA370/socket_fc_pga370.c new file mode 100644 index 0000000..1971714 --- /dev/null +++ b/src/cpu/intel/socket_FC_PGA370/socket_fc_pga370.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui buurin@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +struct chip_operations cpu_intel_socket_fc_pga370_ops = { + CHIP_NAME("Socket FC-PGA370") +}; diff --git a/src/mainboard/packeteer/6500/Kconfig b/src/mainboard/packeteer/6500/Kconfig new file mode 100644 index 0000000..c439257 --- /dev/null +++ b/src/mainboard/packeteer/6500/Kconfig @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Marc Bertens mbertens@xs4all.nl +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if BOARD_PACKETEER_6500 + +config BOARD_SPECIFIC_OPTIONS # PACKETEER_6500 + def_bool y + select CPU_INTEL_SOCKET_FC_PGA370 + select NORTHBRIDGE_INTEL_I440BX + select SOUTHBRIDGE_INTEL_I82371EB + select SUPERIO_SMSC_SMSCSUPERIO + select BOARD_ROMSIZE_KB_512 + select PIRQ_ROUTE + select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES + select ARCH_X86 +# select SDRAMPWR_4DIMM + +config MAINBOARD_DIR + string + default "packeteer/6500" + +config MAINBOARD_PART_NUMBER + string + default "6500" + +config IRQ_SLOT_COUNT + int + default 22 + +endif # BOARD_PACKETEER_6500 diff --git a/src/mainboard/packeteer/6500/Kconfig.name b/src/mainboard/packeteer/6500/Kconfig.name new file mode 100644 index 0000000..5339b80 --- /dev/null +++ b/src/mainboard/packeteer/6500/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_PACKETEER_6500 + bool "6500 Series" diff --git a/src/mainboard/packeteer/6500/Makefile.inc b/src/mainboard/packeteer/6500/Makefile.inc new file mode 100644 index 0000000..979839b --- /dev/null +++ b/src/mainboard/packeteer/6500/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += bootblock.c +ramstage-y += irq_tables.c diff --git a/src/mainboard/packeteer/6500/acpi_tables.c b/src/mainboard/packeteer/6500/acpi_tables.c new file mode 100644 index 0000000..b35610a --- /dev/null +++ b/src/mainboard/packeteer/6500/acpi_tables.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* mainboard has no ioapic */ + return current; +} diff --git a/src/mainboard/packeteer/6500/bootblock.c b/src/mainboard/packeteer/6500/bootblock.c new file mode 100644 index 0000000..217ee1f --- /dev/null +++ b/src/mainboard/packeteer/6500/bootblock.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <superio/smsc/smscsuperio/smscsuperio.h> + +#define SUPERIO_PNP_BASE 0x370 +#define SERIAL_DEV PNP_DEV(SUPERIO_PNP_BASE, SMSCSUPERIO_SP1) + +void bootblock_mainboard_early_init(void) +{ + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/packeteer/6500/devicetree.cb b/src/mainboard/packeteer/6500/devicetree.cb new file mode 100644 index 0000000..7d61df3 --- /dev/null +++ b/src/mainboard/packeteer/6500/devicetree.cb @@ -0,0 +1,117 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Marc Bertens mbertens@xs4all.nl +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i440bx # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_FC_PGA370 # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878) + device pnp 370.0 on + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 370.3 off end + device pnp 370.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 370.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 370.6 on + io 0x63 = 0x70 + irq 0x70 = 8 + end + device pnp 370.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 370.8 off +# irq 0xb0 = 0x00 +# irq 0xb1 = 0x80 +# irq 0xb2 = 0x00 +# irq 0xb3 = 0x00 +# irq 0xb8 = 0x00 +# irq 0xc0 = 0xcf +# irq 0xc1 = 0x03 +# irq 0xc2 = 0x00 +# irq 0xc3 = 0x81 +# irq 0xc4 = 0x00 +# irq 0xc5 = 0x00 +# irq 0xc6 = 0x00 +# irq 0xc8 = 0x01 +# irq 0xca = 0x09 +# irq 0xcb = 0x01 +# irq 0xcc = 0x08 +# irq 0xd0 = 0x08 +# irq 0xd1 = 0x08 +# irq 0xd2 = 0x08 +# irq 0xd3 = 0x08 +# irq 0xd4 = 0x08 +# irq 0xd5 = 0x08 +# irq 0xd6 = 0x01 +# irq 0xd7 = 0x08 +# irq 0xe0 = 0x01 +# irq 0xe1 = 0x01 +# irq 0xe2 = 0x01 +# irq 0xe3 = 0x01 +# irq 0xe4 = 0x01 +# irq 0xe5 = 0x00 +# irq 0xe6 = 0x01 +# irq 0xe7 = 0x01 +# irq 0xef = 0x00 +# irq 0xf0 = 0x00 +# irq 0xf1 = 0x00 +# irq 0xf2 = 0x00 +# irq 0xf3 = 0x00 +# irq 0xf4 = 0x21 +# irq 0xf6 = 0x20 +# irq 0xf9 = 0x18 +# irq 0xfa = 0xbf + end + device pnp 370.A off end # ACPI + end + end + device pci 7.1 on end # IDE + device pci 7.2 on + end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" + register "usb_enable" = "0" +# register "thrm_polarity" = "1" +# register "lid_polarity" = "1" +# register "gpo" = "0x7fffbfff" +## 0x7fffbfff -> DEFAULT POWER ON? + end + end +end diff --git a/src/mainboard/packeteer/6500/dsdt.asl b/src/mainboard/packeteer/6500/dsdt.asl new file mode 100644 index 0000000..b314a31 --- /dev/null +++ b/src/mainboard/packeteer/6500/dsdt.asl @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/i82371eb/i82371eb.h> + +#define SUPERIO_CHIP_NAME SMSCSUPERIO +#define SUPERIO_KBC_LDN 7 +#define SUPERIO_UART_LDN 5 + +#define SUPERIO_PNP_BASE 0x370 +#define SUPERIO_SHOW_UARTA +#define SUPERIO_SHOW_UARTB + +#include <acpi/acpi.h> + +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 1 + ) +{ + #include <arch/x86/acpi/globutil.asl> + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + + OperationRegion(X80, SystemIO, 0x80, 1) + Field(X80, ByteAcc, NoLock, Preserve) + { + P80, 8 + } + + #include <acpi/dsdt_top.asl> + /* _SB scope defining the main processor is generated in SSDT. */ + + #include <arch/x86/acpi/post.asl> + + /* + * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 + * + * 0: soft off/suspend to disk S5 + * 1: suspend to ram S3 + * 2: powered on suspend, context lost S2 + * Note: 'context lost' means the CPU restarts at the reset + * vector + * 3: powered on suspend, CPU context lost S1 + * Note: Looks like 'CPU context lost' does _not_ mean the + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to ACPI S1 + * 4: powered on suspend, context maintained S1 + * 5: working (clock control) S0 + * 6: reserved + * 7: reserved + */ + Name (_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) + Name (_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) + Name (_S5, Package () { 0x00, 0x00, 0x00, 0x00 }) + + /* Prepare To Sleep, Arg0 is target S-state */ + Method (_PTS, 1, NotSerialized) + { + /* Disable fan, blink power LED, if not turning off */ + If (Arg0 != 0x05) + { + //FANM = 0 + //PLED = 0 + } + + /* Arms SMI for device 12 */ + //TO12 = 1 + /* Put out a POST code */ + DBG0 = Arg0 | 0xF0 + } + + Method (_WAK, 1, NotSerialized) + { + /* Re-enable fan, stop power led blinking */ + //FANM = 1 + //PLED = 1 + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) + } + + /* Root of the bus hierarchy */ + Scope (_SB) + { + Method(OSFL, 0){ + + if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + + if(CondRefOf(_OSI)) + { + Store(1, OSVR) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSVR) + } + } else { + If(WCMP(_OS,"Linux")) { + Store(3, OSVR) /* Linux */ + } Else { + Store(4, OSVR) /* Gotta be WinCE */ + } + } + Return(OSVR) + } + + #include <southbridge/intel/i82371eb/acpi/intx.asl> + + PCI_INTX_DEVA(LNKA, _SB.PCI0.PX40.PIRA, 1) + PCI_INTX_DEVB(LNKB, _SB.PCI0.PX40.PIRB, 2) + PCI_INTX_DEVC(LNKC, _SB.PCI0.PX40.PIRC, 3) + PCI_INTX_DEVD(LNKD, _SB.PCI0.PX40.PIRD, 4) + + /* Top PCI device */ + Device (PCI0) + { +// Name(_HID,EISAID("PNP0A08")) // PCIe +// Name(_CID,EISAID("PNP0A03")) // PCI + + Name (_HID, EisaId ("PNP0A03")) + Name (_CID,EISAID("PNP0A08")) // PCIe + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, + + Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, + + Package (0x04) { 0x0011FFFF, 0, LNKC, 0 }, + Package (0x04) { 0x0011FFFF, 1, LNKD, 0 }, + Package (0x04) { 0x0011FFFF, 2, LNKA, 0 }, + Package (0x04) { 0x0011FFFF, 3, LNKB, 0 }, + + Package (0x04) { 0x0012FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0012FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0012FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0012FFFF, 3, LNKC, 0 }, + + Package (0x04) { 0x0007FFFF, 3, LNKD, 0 }, + }) + #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> + #include <southbridge/intel/i82371eb/acpi/isabridge.asl> + + #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> + #include <drivers/pc80/pc/ps2_controller.asl> +// #include <superio/smsc/smscsuperio/acpi/superio.asl> +// #include <superio/acpi/pnp_uart.asl> + } + } + + /* ACPI Message */ + Scope (_SI) + { + Method (_MSG, 1, NotSerialized) + { + If (Arg0 == 0) + { + //MSG0 = 1 + } + Else + { + //MSG0 = 0 + } + } + } +} diff --git a/src/mainboard/packeteer/6500/dsdt.asl2 b/src/mainboard/packeteer/6500/dsdt.asl2 new file mode 100644 index 0000000..b314a31 --- /dev/null +++ b/src/mainboard/packeteer/6500/dsdt.asl2 @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/i82371eb/i82371eb.h> + +#define SUPERIO_CHIP_NAME SMSCSUPERIO +#define SUPERIO_KBC_LDN 7 +#define SUPERIO_UART_LDN 5 + +#define SUPERIO_PNP_BASE 0x370 +#define SUPERIO_SHOW_UARTA +#define SUPERIO_SHOW_UARTB + +#include <acpi/acpi.h> + +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 1 + ) +{ + #include <arch/x86/acpi/globutil.asl> + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + + OperationRegion(X80, SystemIO, 0x80, 1) + Field(X80, ByteAcc, NoLock, Preserve) + { + P80, 8 + } + + #include <acpi/dsdt_top.asl> + /* _SB scope defining the main processor is generated in SSDT. */ + + #include <arch/x86/acpi/post.asl> + + /* + * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 + * + * 0: soft off/suspend to disk S5 + * 1: suspend to ram S3 + * 2: powered on suspend, context lost S2 + * Note: 'context lost' means the CPU restarts at the reset + * vector + * 3: powered on suspend, CPU context lost S1 + * Note: Looks like 'CPU context lost' does _not_ mean the + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to ACPI S1 + * 4: powered on suspend, context maintained S1 + * 5: working (clock control) S0 + * 6: reserved + * 7: reserved + */ + Name (_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) + Name (_S1, Package () { 0x03, 0x03, 0x00, 0x00 }) + Name (_S5, Package () { 0x00, 0x00, 0x00, 0x00 }) + + /* Prepare To Sleep, Arg0 is target S-state */ + Method (_PTS, 1, NotSerialized) + { + /* Disable fan, blink power LED, if not turning off */ + If (Arg0 != 0x05) + { + //FANM = 0 + //PLED = 0 + } + + /* Arms SMI for device 12 */ + //TO12 = 1 + /* Put out a POST code */ + DBG0 = Arg0 | 0xF0 + } + + Method (_WAK, 1, NotSerialized) + { + /* Re-enable fan, stop power led blinking */ + //FANM = 1 + //PLED = 1 + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) + } + + /* Root of the bus hierarchy */ + Scope (_SB) + { + Method(OSFL, 0){ + + if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + + if(CondRefOf(_OSI)) + { + Store(1, OSVR) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSVR) + } + } else { + If(WCMP(_OS,"Linux")) { + Store(3, OSVR) /* Linux */ + } Else { + Store(4, OSVR) /* Gotta be WinCE */ + } + } + Return(OSVR) + } + + #include <southbridge/intel/i82371eb/acpi/intx.asl> + + PCI_INTX_DEVA(LNKA, _SB.PCI0.PX40.PIRA, 1) + PCI_INTX_DEVB(LNKB, _SB.PCI0.PX40.PIRB, 2) + PCI_INTX_DEVC(LNKC, _SB.PCI0.PX40.PIRC, 3) + PCI_INTX_DEVD(LNKD, _SB.PCI0.PX40.PIRD, 4) + + /* Top PCI device */ + Device (PCI0) + { +// Name(_HID,EISAID("PNP0A08")) // PCIe +// Name(_CID,EISAID("PNP0A03")) // PCI + + Name (_HID, EisaId ("PNP0A03")) + Name (_CID,EISAID("PNP0A08")) // PCIe + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, + + Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, + + Package (0x04) { 0x0011FFFF, 0, LNKC, 0 }, + Package (0x04) { 0x0011FFFF, 1, LNKD, 0 }, + Package (0x04) { 0x0011FFFF, 2, LNKA, 0 }, + Package (0x04) { 0x0011FFFF, 3, LNKB, 0 }, + + Package (0x04) { 0x0012FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0012FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0012FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0012FFFF, 3, LNKC, 0 }, + + Package (0x04) { 0x0007FFFF, 3, LNKD, 0 }, + }) + #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> + #include <southbridge/intel/i82371eb/acpi/isabridge.asl> + + #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> + #include <drivers/pc80/pc/ps2_controller.asl> +// #include <superio/smsc/smscsuperio/acpi/superio.asl> +// #include <superio/acpi/pnp_uart.asl> + } + } + + /* ACPI Message */ + Scope (_SI) + { + Method (_MSG, 1, NotSerialized) + { + If (Arg0 == 0) + { + //MSG0 = 1 + } + Else + { + //MSG0 = 0 + } + } + } +} diff --git a/src/mainboard/packeteer/6500/irq_tables.c b/src/mainboard/packeteer/6500/irq_tables.c new file mode 100644 index 0000000..54afc56 --- /dev/null +++ b/src/mainboard/packeteer/6500/irq_tables.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Bertens mbertens@xs4all.nl + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/pirq_routing.h> + +#define PIRQ_IRQ_MASK 0x0E20 + +#define PIRQ_INT_A 0x62 +#define PIRQ_INT_B 0x61 +#define PIRQ_INT_C 0x60 +#define PIRQ_INT_D 0x63 + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xBC, /* Checksum */ + { + // NONE + //{ 0x00, (0x04 << 3) | 0x0, {{PIRQ_INT_D, PIRQ_IRQ_MASK}, {PIRQ_INT_A, PIRQ_IRQ_MASK}, {PIRQ_INT_C, PIRQ_IRQ_MASK}, {PIRQ_INT_B, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + + // Southbridge 82371 + { 0x00, (0x07 << 3) | 0x0, {{0x00, 0x0}, {0x00, 0x0}, {0x00, 0x0}, {PIRQ_INT_D, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + //{ 0x00, (0x01 << 3) | 0x0, {{PIRQ_INT_A, PIRQ_IRQ_MASK}, {PIRQ_INT_B, PIRQ_IRQ_MASK}, {PIRQ_INT_C, PIRQ_IRQ_MASK}, {PIRQ_INT_D, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + + // PCI slot (bottom) + { 0x00, (0x11 << 3) | 0x0, {{PIRQ_INT_A, PIRQ_IRQ_MASK}, {PIRQ_INT_D, PIRQ_IRQ_MASK}, {PIRQ_INT_C, PIRQ_IRQ_MASK}, {PIRQ_INT_B, PIRQ_IRQ_MASK}}, 0x1, 0x0 }, + + // ETH0 (front panel left) + { 0x00, (0x0b << 3) | 0x0, {{PIRQ_INT_B, PIRQ_IRQ_MASK}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x0}}, 0x0, 0x0 }, + + // ETH1 (front panel right) + { 0x00, (0x0c << 3) | 0x0, {{PIRQ_INT_C, PIRQ_IRQ_MASK}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x0}}, 0x0, 0x0 }, + + // PCI slot (top) + { 0x00, (0x12 << 3) | 0x0, {{PIRQ_INT_D, PIRQ_IRQ_MASK}, {PIRQ_INT_C, PIRQ_IRQ_MASK}, {PIRQ_INT_B, PIRQ_IRQ_MASK}, {PIRQ_INT_A, PIRQ_IRQ_MASK}}, 0x2, 0x0 }, + + // PCI slot (top) + //{ 0x01, (0x00 << 3) | 0x0, {{PIRQ_INT_D, PIRQ_IRQ_MASK}, {PIRQ_INT_C, PIRQ_IRQ_MASK}, {PIRQ_INT_B, PIRQ_IRQ_MASK}, {PIRQ_INT_A, PIRQ_IRQ_MASK}}, 0x1, 0x0 }, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} + +/** + * TODO: This stub function is here until the point is solved in the + * main code of coreboot. See also arch/x86/boot/pirq_tables.c. + */ +void pirq_assign_irqs(const unsigned char pIntAtoD[4]) +{ + return; +} diff --git a/src/mainboard/packeteer/6500/irq_tables.c_ok b/src/mainboard/packeteer/6500/irq_tables.c_ok new file mode 100644 index 0000000..0512dfa --- /dev/null +++ b/src/mainboard/packeteer/6500/irq_tables.c_ok @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Bertens mbertens@xs4all.nl + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/pirq_routing.h> + +#define PIRQ_IRQ_MASK 0x0E20 + +#define PIRQ_INT_A 0x62 +#define PIRQ_INT_B 0x61 +#define PIRQ_INT_C 0x60 +#define PIRQ_INT_D 0x63 + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x5E, /* Checksum */ + { + // NONE + //{ 0x00, (0x04 << 3) | 0x0, {{PIRQ_INT_D, PIRQ_IRQ_MASK}, {PIRQ_INT_A, PIRQ_IRQ_MASK}, {PIRQ_INT_C, PIRQ_IRQ_MASK}, {PIRQ_INT_B, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + + // Southbridge 82371 + { 0x00, (0x07 << 3) | 0x0, {{0x00, 0x0}, {0x00, 0x0}, {0x00, 0x0}, {PIRQ_INT_D, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + //{ 0x00, (0x01 << 3) | 0x0, {{PIRQ_INT_A, PIRQ_IRQ_MASK}, {PIRQ_INT_B, PIRQ_IRQ_MASK}, {PIRQ_INT_C, PIRQ_IRQ_MASK}, {PIRQ_INT_D, PIRQ_IRQ_MASK}}, 0x0, 0x0 }, + + // PCI slot (bottom) + { 0x00, (0x11 << 3) | 0x0, {{PIRQ_INT_A, PIRQ_IRQ_MASK}, {PIRQ_INT_D, PIRQ_IRQ_MASK}, {PIRQ_INT_C, PIRQ_IRQ_MASK}, {PIRQ_INT_B, PIRQ_IRQ_MASK}}, 0x1, 0x0 }, + + // ETH0 (front panel left) + { 0x00, (0x0b << 3) | 0x0, {{PIRQ_INT_B, PIRQ_IRQ_MASK}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x0}}, 0x0, 0x0 }, + + // ETH1 (front panel right) + { 0x00, (0x0c << 3) | 0x0, {{PIRQ_INT_C, PIRQ_IRQ_MASK}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x0}}, 0x0, 0x0 }, + + // PCI slot (top) + { 0x00, (0x12 << 3) | 0x0, {{PIRQ_INT_D, PIRQ_IRQ_MASK}, {PIRQ_INT_C, PIRQ_IRQ_MASK}, {PIRQ_INT_B, PIRQ_IRQ_MASK}, {PIRQ_INT_A, PIRQ_IRQ_MASK}}, 0x2, 0x0 }, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} + +/** + * TODO: This stub function is here until the point is solved in the + * main code of coreboot. See also arch/x86/boot/pirq_tables.c. + */ +void pirq_assign_irqs(const unsigned char pIntAtoD[4]) +{ + return; +} diff --git a/src/mainboard/packeteer/6500/mainboard.c b/src/mainboard/packeteer/6500/mainboard.c new file mode 100644 index 0000000..1e12c18 --- /dev/null +++ b/src/mainboard/packeteer/6500/mainboard.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <southbridge/intel/i82371eb/i82371eb.h> +//#include <delay.h> + +/** + * Mainboard specific enables. + * + * @param chip_info Ignored + */ +static void mainboard_init(void *chip_info) +{ + // Sleep 5 seconds in order for the motherboard to settle +// delay(5); +// const pci_devfn_t px43 = PCI_DEV(0, 7, 3); +// u32 reg; + /* + * Set up an 8-byte generic I/O decode block at device 9. + * This will be for W83781D hardware monitor. + * Port 0x290 mask 0x007 + * + * This should enable access to W83781D over the ISA bus. + */ +// reg = pci_s_read_config32(px43, DEVRESB); +// reg |= (0x290 | (0xe7 << 16)); +// pci_s_write_config32(px43, DEVRESB, reg); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init +}; diff --git a/src/mainboard/packeteer/6500/superio.asl b/src/mainboard/packeteer/6500/superio.asl new file mode 100644 index 0000000..eda6744 --- /dev/null +++ b/src/mainboard/packeteer/6500/superio.asl @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include this file into a southbridge ASL block and it will + * expose the W83977TF/EF SuperIO and some of its functionality. + * + * Adapted from winbond/w83627dhg. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * Controllable through preprocessor defines: + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * SUPERIO_SHOW_UARTA If defined, UARTA will be exposed. + * SUPERIO_SHOW_UARTB If defined, UARTB will be exposed. + * SUPERIO_SHOW_FDC If defined, floppy controller will be exposed. + * SUPERIO_SHOW_LPT If defined, parallel port will be exposed. + */ + +#define SUPERIO_CHIP_NAME W83977TF +#include <superio/acpi/pnp.asl> +#include <superio/winbond/w83977tf/w83977tf.h> + +/* Mutex for accesses to the configuration ports */ + +Mutex(CRMX, 1) + +/* SuperIO configuration ports */ +OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) +Field (CREG, ByteAcc, NoLock, Preserve) +{ + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 +} +IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) +{ + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + Offset (0x20), + DID, 8, /* Device ID: TF=0x97, EF=0x52 */ + DREV, 8, /* Device revision */ + FDPW, 1, + , 2, + PRPW, 1, + UAPW, 1, /* UART A Power Down */ + UBPW, 1, /* UART B Power Down */ + Offset (0x23), + IPD, 1, /* Immediate Chip Power Down */ + Offset (0x30), + PNP_DEVICE_ACTIVE, 8, + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, + PNP_IO0_LOW_BYTE, 8, + PNP_IO1_HIGH_BYTE, 8, + PNP_IO1_LOW_BYTE, 8, + PNP_IO2_HIGH_BYTE, 8, + PNP_IO2_LOW_BYTE, 8, + Offset (0x70), + PNP_IRQ0, 8, + Offset (0x72), + PNP_IRQ1, 8, + Offset (0x74), + PNP_DMA0, 8, + /* MSWK and KBWK are for ACPI logical device, LDN 0xA */ + Offset (0xE0), + MSWK, 8, + Offset (0xE4), + KBWK, 8, + Offset (0xF0), + OPT1, 8, + OPT2, 8 +} + +#define PNP_ENTER_MAGIC_1ST 0x87 +#define PNP_ENTER_MAGIC_2ND 0x87 +#define PNP_EXIT_MAGIC_1ST 0xaa +#include <superio/acpi/pnp_config.asl> + +/* PM: indicate IPD (Immediate Power Down) bit state as D0/D3 */ +Method (_PSC) { + ENTER_CONFIG_MODE (PNP_NO_LDN_CHANGE) + Local0 = IPD + EXIT_CONFIG_MODE () + If (Local0) { Return (3) } + Else { Return (0) } +} + +#ifdef SUPERIO_SHOW_FDC +Device (FDC0) +{ + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + PNP_GENERIC_STA(W83977TF_FDC) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PNP_GENERIC_DIS(W83977TF_FDC) + } + + Method (_CRS, 0) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04, IO0) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01, IO1) + IRQ (Edge, ActiveHigh, Exclusive, Y08) {6} + DMA (Compatibility, NotBusMaster, Transfer8, Y09) {2} + }) + CreateWordField (BUF0, IO1._MIN, IO1I) + CreateWordField (BUF0, IO1._MAX, IO1A) + + ENTER_CONFIG_MODE(W83977TF_FDC) + /* OEM BIOS does not report actual programmed base port */ + /* xx0 is read from superio */ + PNP_READ_IO(PNP_IO0, BUF0, IO0) + /* Store xx7 range first so the value isn't overwritten + * for below */ + IO1I += 7 + IO1A = IO1I + /* Store xx2 range */ + IO0I += 2 + IO0A = IO0I + /* End OEM BIOS deficiency */ + PNP_READ_IRQ(PNP_IRQ0, BUF0, Y08) + PNP_READ_DMA(PNP_DMA0, BUF0, Y09) + + EXIT_CONFIG_MODE() + Return (BUF0) + } + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04, ) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01, ) + IRQ (Edge, ActiveHigh, Exclusive, ) {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) {2} + }) + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x02, IOLO) + CreateByteField (Arg0, 0x03, IOHI) + CreateWordField (Arg0, 0x11, IRQW) + CreateByteField (Arg0, 0x15, DMAV) + ENTER_CONFIG_MODE(W83977TF_FDC) + /* FDC base port on 8-byte boundary. */ + PNP_IO0_LOW_BYTE = IOLO & 0xF8 + PNP_IO0_HIGH_BYTE = IOHI + PNP_IRQ0 = FindSetLeftBit (IRQW) - 1 + PNP_DMA0 = FindSetLeftBit (DMAV) - 1 + PNP_DEVICE_ACTIVE = 1 + EXIT_CONFIG_MODE() + } +} +#endif + +#ifdef SUPERIO_SHOW_LPT +/* Standard LPT Parallel Port */ +Device (LPT) +{ + Name (_HID, EisaId ("PNP0400")) + Method (_STA, 0, NotSerialized) + { + ENTER_CONFIG_MODE(W83977TF_PP) + Local0 = OPT1 & 0x02 + If (IO0H || IO0L) + { + /* Report device not present if ECP is enabled */ + If (Local0 == 0x02) + { + EXIT_CONFIG_MODE() + Return (0x00) + } + ElseIf (PNP_DEVICE_ACTIVE) + { + EXIT_CONFIG_MODE() + Return (0x0F) + } + Else + { + EXIT_CONFIG_MODE() + Return (0x0D) + } + } + + EXIT_CONFIG_MODE() + Return (0) + } + + Method (_DIS, 0, NotSerialized) + { + PNP_GENERIC_DIS(W83977TF_PP) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF5, ResourceTemplate () + { + IO (Decode16,0x0378,0x0378,0x00,0x04,Y0A) + IRQ (Edge, ActiveHigh, Exclusive, Y0B) + {7} + }) + ENTER_CONFIG_MODE(W83977TF_PP) + PNP_READ_IO(PNP_IO0,BUF5,Y0A) + PNP_READ_IRQ(PNP_IRQ0,BUF5,Y0B) + EXIT_CONFIG_MODE() + Return (BUF5) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x0378,0x0378,0x00,0x08,) + IRQ (Edge, ActiveHigh, Exclusive, ) + {5,7} + } + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x0278,0x0278,0x00,0x08,) + IRQ (Edge, ActiveHigh, Exclusive, ) + {5,7} + } + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x03BC,0x03BC,0x00,0x04,) + IRQ (Edge, ActiveHigh, Exclusive, ) + {5,7} + } + EndDependentFn () + }) + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x02, IOLO) + CreateByteField (Arg0, 0x03, IOHI) + CreateWordField (Arg0, 0x09, IRQW) + ENTER_CONFIG_MODE(W83977TF_PP) + PNP_IO0_LOW_BYTE = IOLO + PNP_IO0_HIGH_BYTE = IOHI + PNP_IRQ0 = FindSetLeftBit (IRQW) - 1 + PNP_DEVICE_ACTIVE = 1 + EXIT_CONFIG_MODE() + } +} + +/* ECP Parallel Port */ +Device (ECP) +{ + Name (_HID, EisaId ("PNP0401")) + Method (_STA, 0, NotSerialized) + { + ENTER_CONFIG_MODE(W83977TF_PP) + Local0 = OPT1 & 0x02 + If (IO0H || IO0L) + { + If (Local0 == 0x02) + { + If (PNP_DEVICE_ACTIVE) + { + EXIT_CONFIG_MODE() + Return (0x0F) + } + Else + { + EXIT_CONFIG_MODE() + Return (0x05) + } + } + } + + EXIT_CONFIG_MODE() + Return (0x00) + } + + Method (_DIS, 0, NotSerialized) + { + PNP_GENERIC_DIS(W83977TF_PP) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF6, ResourceTemplate () + { + IO (Decode16,0x0378,0x0378,0,4,IO0) + IO (Decode16,0x0778,0x0778,0,4,IO1) + IRQ (Edge, ActiveHigh, Exclusive, IR1) {7} + DMA (Compatibility, NotBusMaster, Transfer8, Y0F) {1} + }) + ENTER_CONFIG_MODE(W83977TF_PP) + PNP_READ_IO(PNP_IO0, BUF6, IO0) + PNP_READ_IO(PNP_IO0, BUF6, IO1) + PNP_READ_IRQ(PNP_IRQ0, BUF6, IR1) + PNP_READ_DMA(PNP_DMA0, BUF6, Y0F) + + /* Report a second port range that is 0x400 above base port. */ + CreateByteField (BUF6, 0x0B, I2HI) + CreateByteField (BUF6, 0x0D, I2RH) + I2RH = I2HI + 4 + I2HI = I2HI + 4 + EXIT_CONFIG_MODE() + Return (BUF6) + } + + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x0378,0x0378,0,4,) + IO (Decode16,0x0778,0x0778,0,4,) + IRQ (Edge, ActiveHigh, Exclusive, ) {5,7} + DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3} + } + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x0278,0x0278,0,4,) + IO (Decode16,0x0678,0x0678,0,4,) + IRQ (Edge, ActiveHigh, Exclusive, ) {5,7} + DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3} + } + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x03BC,0x03BC,0,4,) + IO (Decode16,0x07BC,0x07BC,0,4,) + IRQ (Edge, ActiveHigh, Exclusive, ) {5,7} + DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3} + } + EndDependentFn () + }) + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateByteField (Arg0, 0x02, IOLO) + CreateByteField (Arg0, 0x03, IOHI) + CreateWordField (Arg0, 0x11, IRQW) + CreateByteField (Arg0, 0x15, DMAC) + + ENTER_CONFIG_MODE(W83977TF_PP) + PNP_IO0_LOW_BYTE = IOLO + PNP_IO0_HIGH_BYTE = IOHI + PNP_IRQ0 = FindSetLeftBit (IRQW) - 1 + PNP_DMA0 = FindSetLeftBit (DMAC) - 1 + PNP_DEVICE_ACTIVE = 1 + EXIT_CONFIG_MODE() + } +} +#endif + +#define SUPERIO_UART_PM_VAL 0 +#define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + +#ifdef SUPERIO_SHOW_UARTA + #define SUPERIO_UART_LDN W83977TF_SP1 + #define SUPERIO_UART_PM_REG UAPW + #include <superio/acpi/pnp_uart.asl> + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_PM_REG +#endif + +#ifdef SUPERIO_SHOW_UARTB + #define SUPERIO_UART_LDN W83977TF_SP2 + #define SUPERIO_UART_PM_REG UBPW + #include <superio/acpi/pnp_uart.asl> + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_PM_REG +#endif + +/* + * TODO: IrDA device; + * EF=LDN 3 aka UARTB + * Some revisions of TF=LDN 6 + */ + +#define SUPERIO_KBC_LDN W83977TF_KBC +#define SUPERIO_KBC_PS2M /* Mouse shares same LDN */ +#include <superio/acpi/pnp_kbc.asl> diff --git a/src/mainboard/packeteer/Kconfig b/src/mainboard/packeteer/Kconfig new file mode 100644 index 0000000..0aff62b --- /dev/null +++ b/src/mainboard/packeteer/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_PACKETEER + +choice + prompt "Mainboard model" + +source "src/mainboard/packeteer/*/Kconfig.name" + +endchoice + +source "src/mainboard/packeteer/*/Kconfig" + +config MAINBOARD_VENDOR + default "Packeteer" + +endif # VENDOR_PACKETEER diff --git a/src/mainboard/packeteer/Kconfig.name b/src/mainboard/packeteer/Kconfig.name new file mode 100644 index 0000000..a4f8293 --- /dev/null +++ b/src/mainboard/packeteer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_PACKETEER + bool "Packeteer" diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index e3e67ea..cc81855 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -5,7 +5,7 @@ /* Declares assorted devices that fall under this southbridge. */ Device (PX40) { - Name(_ADR, 0x00040000) + Name(_ADR, 0x00070000) OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) Field (PIRQ, ByteAcc, NoLock, Preserve) { @@ -86,18 +86,14 @@ IRQNoFlags () {0} }) } - /* AT Real-Time Clock */ - Device (RTC) - { - Name (_HID, EisaId ("PNP0B00")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16,0x0070,0x0070,0x01,0x04,) - IRQNoFlags () {8} - }) - } - + Device(RTC) { + Name(_HID, EISAID("PNP0B00")) + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO (Decode16,0x0070,0x0070,0x01,0x04,) + }) + } Device (SPKR) { Name (_HID, EisaId ("PNP0800")) @@ -120,7 +116,7 @@ } Device (PX43) { - Name (_ADR, 0x00040003) // _ADR: Address + Name (_ADR, 0x00070003) // _ADR: Address
Method (_CRS, 0, NotSerialized) { diff --git a/src/southbridge/intel/i82371eb/acpi/intx.asl b/src/southbridge/intel/i82371eb/acpi/intx.asl index f4fa928..092e79f 100644 --- a/src/southbridge/intel/i82371eb/acpi/intx.asl +++ b/src/southbridge/intel/i82371eb/acpi/intx.asl @@ -4,7 +4,20 @@ })
Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){3, 4, 5, 6, 7, 10, 11, 12, 14, 15} + IRQ(Level,ActiveLow,Shared){3, 4, 5, 6, 7, 10, 11, 12} +}) + +Name(IRQT, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){9} +}) +Name(IRQU, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){11} +}) +Name(IRQV, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){10} +}) +Name(IRQW, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){5} })
/* adapted from ma78gm/dsdt.asl */ @@ -45,3 +58,155 @@ Store(Local0, pinx) \ } \ } + +#define PCI_INTX_DEVA(intx, pinx, uid) \ +Device(intx) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + \ + Method(_STA, 0) { \ + If (And(pinx, 0x80)) { \ + Return(0x09) \ + } \ + Return(0x0B) \ + } \ + \ + Method(_DIS ,0) { \ + Store(0x80, pinx) \ + } \ + \ + Method(_PRS ,0) { \ + Return(IRQT) \ + } \ + \ + Method(_CRS ,0) { \ + CreateWordField(IRQB, 1, IRQN) \ + ShiftLeft(1, And(pinx, 0x0f), IRQN) \ + Return(IRQB) \ + } \ + \ + Method(_SRS, 1) { \ + CreateWordField(ARG0, 1, IRQM) \ + \ + /* Use lowest available IRQ */ \ + FindSetRightBit(IRQM, Local0) \ + if (Local0) { \ + Local0-- \ + } \ + Store(Local0, pinx) \ + } \ +} + +#define PCI_INTX_DEVB(intx, pinx, uid) \ +Device(intx) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + \ + Method(_STA, 0) { \ + If (And(pinx, 0x80)) { \ + Return(0x09) \ + } \ + Return(0x0B) \ + } \ + \ + Method(_DIS ,0) { \ + Store(0x80, pinx) \ + } \ + \ + Method(_PRS ,0) { \ + Return(IRQU) \ + } \ + \ + Method(_CRS ,0) { \ + CreateWordField(IRQB, 1, IRQN) \ + ShiftLeft(1, And(pinx, 0x0f), IRQN) \ + Return(IRQB) \ + } \ + \ + Method(_SRS, 1) { \ + CreateWordField(ARG0, 1, IRQM) \ + \ + /* Use lowest available IRQ */ \ + FindSetRightBit(IRQM, Local0) \ + if (Local0) { \ + Local0-- \ + } \ + Store(Local0, pinx) \ + } \ +} + +#define PCI_INTX_DEVC(intx, pinx, uid) \ +Device(intx) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + \ + Method(_STA, 0) { \ + If (And(pinx, 0x80)) { \ + Return(0x09) \ + } \ + Return(0x0B) \ + } \ + \ + Method(_DIS ,0) { \ + Store(0x80, pinx) \ + } \ + \ + Method(_PRS ,0) { \ + Return(IRQV) \ + } \ + \ + Method(_CRS ,0) { \ + CreateWordField(IRQB, 1, IRQN) \ + ShiftLeft(1, And(pinx, 0x0f), IRQN) \ + Return(IRQB) \ + } \ + \ + Method(_SRS, 1) { \ + CreateWordField(ARG0, 1, IRQM) \ + \ + /* Use lowest available IRQ */ \ + FindSetRightBit(IRQM, Local0) \ + if (Local0) { \ + Local0-- \ + } \ + Store(Local0, pinx) \ + } \ +} + +#define PCI_INTX_DEVD(intx, pinx, uid) \ +Device(intx) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + \ + Method(_STA, 0) { \ + If (And(pinx, 0x80)) { \ + Return(0x09) \ + } \ + Return(0x0B) \ + } \ + \ + Method(_DIS ,0) { \ + Store(0x80, pinx) \ + } \ + \ + Method(_PRS ,0) { \ + Return(IRQW) \ + } \ + \ + Method(_CRS ,0) { \ + CreateWordField(IRQB, 1, IRQN) \ + ShiftLeft(1, And(pinx, 0x0f), IRQN) \ + Return(IRQB) \ + } \ + \ + Method(_SRS, 1) { \ + CreateWordField(ARG0, 1, IRQM) \ + \ + /* Use lowest available IRQ */ \ + FindSetRightBit(IRQM, Local0) \ + if (Local0) { \ + Local0-- \ + } \ + Store(Local0, pinx) \ + } \ +} diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index c5329f4..c17a289 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -22,7 +22,7 @@ struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
/* Initialize the real time clock (RTC). */ - cmos_init(0); + cmos_init(1);
/* * Enable special cycles, needed for soft poweroff.