[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/xeon_sp: Report RCiEPs under DRHD

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Hello Jincheng Li,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/84315?usp=email

to review the following change.

Change subject: soc/intel/xeon_sp: Report RCiEPs under DRHD
......................................................................

soc/intel/xeon_sp: Report RCiEPs under DRHD

In case of a PCH-less platform, all RCiEPs should be listed under
its specific DRHD

Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa
Signed-off-by: Jincheng Li 
---
M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 16 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84315/1

diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index baffdd0..9ba04fa 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -336,22 +336,22 @@
 #endif
    }

-	// Add IOAT End Points (with memory resources. We don't report every End Point device.)
-	if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(iommu)) {
-		struct device *dev = NULL;
-		while ((dev = dev_find_all_devices_on_stack(socket, stack,
-			XEONSP_VENDOR_MAX, XEONSP_DEVICE_MAX, dev)))
-			/* This may also require a check for IORESOURCE_PREFETCH,
-			 * but that would not include the FPU (4942/0) */
-			if ((dev->resource_list->flags &
-				(IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED)) ==
-				(IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED)) {
-				const uint32_t b = dev->upstream->secondary;
-				const uint32_t d = PCI_SLOT(dev->path.pci.devfn);
-				const uint32_t f = PCI_FUNC(dev->path.pci.devfn);
-				printk(BIOS_DEBUG, "    [PCIE Endpoint Device] %s\n", dev_path(dev));
-				current += acpi_create_dmar_ds_pci(current, b, d, f);
-			}
+	struct device *dev = NULL;
+	while ((dev = dev_find_all_devices_on_stack(socket, stack,
+		XEONSP_VENDOR_MAX, XEONSP_DEVICE_MAX, dev))) {
+		const uint32_t b = dev->upstream->secondary;
+		const uint32_t d = PCI_SLOT(dev->path.pci.devfn);
+		const uint32_t f = PCI_FUNC(dev->path.pci.devfn);
+		struct device *upstream_dev = dev->upstream->dev;
+
+		if (is_pci_bridge(dev))
+			continue;
+
+		if (upstream_dev->path.type != DEVICE_PATH_DOMAIN)
+			continue;
+
+		printk(BIOS_DEBUG, "    [PCIE Endpoint Device] %s\n", dev_path(dev));
+		current += acpi_create_dmar_ds_pci(current, b, d, f);
    }

// Add HPET