Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84244?usp=email )
Change subject: Docs: Revert false MyST Parser toctree conversions ......................................................................
Docs: Revert false MyST Parser toctree conversions
Commit 35599f9a6671 (Docs: Replace Recommonmark with MyST Parser) converted recommonmark style toctrees in bulk using a script. This was done by searching for lists of references, which is how recommonmark denoted toctree entries. However, this also converted lists of external URLs, which would not normally be included in the toctree. Revert these cases back to lists of URLs as they were before the migration.
Change-Id: Ie4da3d908d4b84c2c7e3572fb4baaeed1f8edb45 Signed-off-by: Nicholas Chin nic.c3.14@gmail.com --- M Documentation/acpi/index.md M Documentation/acronyms.md M Documentation/drivers/smmstore.md M Documentation/drivers/smmstorev2.md M Documentation/external_docs.md M Documentation/getting_started/kconfig.md M Documentation/infrastructure/builders.md M Documentation/mainboard/lenovo/ivb_internal_flashing.md M Documentation/mainboard/protectli/vp2420.md M Documentation/mainboard/protectli/vp46xx.md M Documentation/releases/coreboot-4.17-relnotes.md M Documentation/soc/intel/fit.md M Documentation/soc/intel/fsp/ppi/ppi.md M Documentation/technotes/console.md 14 files changed, 54 insertions(+), 164 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/84244/1
diff --git a/Documentation/acpi/index.md b/Documentation/acpi/index.md index 15d3ddd..4337611 100644 --- a/Documentation/acpi/index.md +++ b/Documentation/acpi/index.md @@ -29,10 +29,6 @@
## ACPI specification - Useful links
-```{toctree} -:maxdepth: 1 - -ACPI Specification 6.5 https://uefi.org/specs/ACPI/6.5/index.html -ASL 2.0 Syntax https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions -Predefined ACPI Names https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names -``` +- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html) +- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-opera...) +- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#pred...) diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md index 8dbb067..2f32b85 100644 --- a/Documentation/acronyms.md +++ b/Documentation/acronyms.md @@ -1141,8 +1141,4 @@
## References: -```{toctree} -:maxdepth: 1 - -AMD Glossary of terms https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-web.pdf -``` +* [AMD Glossary of terms](https://www.amd.com/system/files/documents/glossary-of-terms-20220505-for-we...) diff --git a/Documentation/drivers/smmstore.md b/Documentation/drivers/smmstore.md index d68e51c..c9f0060 100644 --- a/Documentation/drivers/smmstore.md +++ b/Documentation/drivers/smmstore.md @@ -128,11 +128,8 @@
## External links
-```{toctree} -:maxdepth: 1 +* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_b...)
-A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf -``` Note, this differs significantly from coreboot's implementation.
[SMM]: ../security/smm.md diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md index 8e74c93..6956cd4 100644 --- a/Documentation/drivers/smmstorev2.md +++ b/Documentation/drivers/smmstorev2.md @@ -199,11 +199,8 @@
## External links
-```{toctree} -:maxdepth: 1 +* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_b...)
-A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf -``` Note that this differs significantly from coreboot's implementation.
[SMM]: ../security/smm.md diff --git a/Documentation/external_docs.md b/Documentation/external_docs.md index 47c7600..b5ee908 100644 --- a/Documentation/external_docs.md +++ b/Documentation/external_docs.md @@ -17,21 +17,13 @@ * [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initializati...) * [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initializati...) * [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf) -```{toctree} -:maxdepth: 1 - -Boot Guard and PSB have user-hostile defaults https://mjg59.dreamwidth.org/58424.html -``` +* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
## General Information
-```{toctree} -:maxdepth: 1 - -OS Dev https://wiki.osdev.org/Categorized_Main_Page -Interface BUS http://www.interfacebus.com/ -``` +* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page) +* [Interface BUS](http://www.interfacebus.com/)
## OpenSecurityTraining2
@@ -51,14 +43,10 @@ Below is a list of currently available courses that can help understand the inner workings of coreboot and other firmware-related topics:
-```{toctree} -:maxdepth: 1 - -coreboot design principles and boot process https://ost2.fyi/Arch4031 -x86-64 Assembly https://ost2.fyi/Arch1001 -x86-64 OS Internals https://ost2.fyi/Arch2001 -x86-64 Intel Firmware Attack & Defense https://ost2.fyi/Arch4001 -``` +* [coreboot design principles and boot process](https://ost2.fyi/Arch4031) +* [x86-64 Assembly](https://ost2.fyi/Arch1001) +* [x86-64 OS Internals](https://ost2.fyi/Arch2001) +* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
There are [additional security courses](https://p.ost2.fyi/courses) at the site as well (such as @@ -66,79 +54,47 @@
## Firmware Specifications & Information
-```{toctree} -:maxdepth: 1 - -System Management BIOS - SMBIOS https://www.dmtf.org/standards/smbios -Desktop and Mobile Architecture for System Hardware - DASH https://www.dmtf.org/standards/dash -PNP BIOS https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf -``` +* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios) +* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash) +* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/deskt...)
### ACPI
-```{toctree} -:maxdepth: 1 - -ACPI Specs https://uefi.org/acpi/specs -ACPI in Linux https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf -ACPI 5 Linux https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf -ACPI 6 Linux https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf -``` +* [ACPI Specs](https://uefi.org/acpi/specs) +* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf) +* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-A...) +* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Li...)
### Security
-```{toctree} -:maxdepth: 1 - -Intel Boot Guard https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard -``` +* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure...)
## Hardware information
-```{toctree} -:maxdepth: 1 - -WikiChip https://en.wikichip.org/wiki/WikiChip -Sandpile https://www.sandpile.org/ -CPU-World https://www.cpu-world.com/index.html -CPU-Upgrade https://www.cpu-upgrade.com/index.html -``` +* [WikiChip](https://en.wikichip.org/wiki/WikiChip) +* [Sandpile](https://www.sandpile.org/) +* [CPU-World](https://www.cpu-world.com/index.html) +* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
### Hardware Specifications & Standards
* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG -```{toctree} -:maxdepth: 1 - -eMMC <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED> -``` +* [eMMC](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED) * [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel * [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-...), [Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP * [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP -```{toctree} -:maxdepth: 1 - -I3C <https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED> -Memory <https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED> -``` +* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED) +* [Memory](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED) * [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications * [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin...) - Intel -```{toctree} -:maxdepth: 1 - -PCI / PCIe / M.2 <https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED> -``` +* [PCI / PCIe / M.2](https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED) * [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum -```{toctree} -:maxdepth: 1 - -SATA <https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED> -``` +* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED) * [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum * [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum * [USB](https://www.usb.org/documents) - USB Implementers Forum @@ -177,9 +133,5 @@
## Infrastructure software
-```{toctree} -:maxdepth: 1 - -Kconfig https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html -GNU Make https://www.gnu.org/software/make/manual/ -``` +* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html) +* [GNU Make](https://www.gnu.org/software/make/manual/) diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index bff077c..8965458 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -11,12 +11,8 @@
The official Kconfig source and documentation is kept at kernel.org:
-```{toctree} -:maxdepth: 1 - -Kconfig source https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/scripts/kconfig -Kconfig Language Documentation https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt -``` +- [Kconfig source](https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/scripts...) +- [Kconfig Language Documentation](https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt)
The advantage to using Kconfig is that it allows users to easily select the high level features of the project to be enabled or disabled at build time. diff --git a/Documentation/infrastructure/builders.md b/Documentation/infrastructure/builders.md index dc4216d..b200140e 100644 --- a/Documentation/infrastructure/builders.md +++ b/Documentation/infrastructure/builders.md @@ -93,19 +93,11 @@ Most of the time on the builders is taken up by the coreboot main and coreboot gerrit builds.
-```{toctree} -:maxdepth: 1 - -coreboot gerrit build https://qa.coreboot.org/job/coreboot-gerrit/ -``` +* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) ([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
-```{toctree} -:maxdepth: 1 - -coreboot main build https://qa.coreboot.org/job/coreboot/ -``` +* [coreboot main build](https://qa.coreboot.org/job/coreboot/) ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend))
diff --git a/Documentation/mainboard/lenovo/ivb_internal_flashing.md b/Documentation/mainboard/lenovo/ivb_internal_flashing.md index a6004a7..3559481 100644 --- a/Documentation/mainboard/lenovo/ivb_internal_flashing.md +++ b/Documentation/mainboard/lenovo/ivb_internal_flashing.md @@ -19,11 +19,7 @@
- USB drive (in case you need to downgrade BIOS) - Linux install that (can be) loaded in UEFI mode -```{toctree} -:maxdepth: 1 - -CHIPSEC https://github.com/chipsec/chipsec -``` +- [CHIPSEC](https://github.com/chipsec/chipsec)
## BIOS versions
diff --git a/Documentation/mainboard/protectli/vp2420.md b/Documentation/mainboard/protectli/vp2420.md index b5a7ff6..b4ec597 100644 --- a/Documentation/mainboard/protectli/vp2420.md +++ b/Documentation/mainboard/protectli/vp2420.md @@ -80,12 +80,8 @@
## Useful links
-```{toctree} -:maxdepth: 1 - -VP2420 Hardware Overview https://protectli.com/kb/vp2400-series-hardware-overview/ -VP2420 Product Page https://protectli.com/product/vp2420/ -Protectli TPM module https://protectli.com/product/tpm-module/ -MX25L12835F https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf -flashrom https://flashrom.org/Flashrom -``` +- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/) +- [VP2420 Product Page](https://protectli.com/product/vp2420/) +- [Protectli TPM module](https://protectli.com/product/tpm-module/) +- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%...) +- [flashrom](https://flashrom.org/Flashrom) diff --git a/Documentation/mainboard/protectli/vp46xx.md b/Documentation/mainboard/protectli/vp46xx.md index eada7ff..f86f931 100644 --- a/Documentation/mainboard/protectli/vp46xx.md +++ b/Documentation/mainboard/protectli/vp46xx.md @@ -126,13 +126,9 @@
## Useful links
-```{toctree} -:maxdepth: 1 - -VP4600 Hardware Overview https://protectli.com/kb/vp4600-hardware-overview/ -VP4630 Product Page https://protectli.com/product/vp4630/ -Protectli TPM module https://protectli.com/product/tpm-module/ -``` +- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/) +- [VP4630 Product Page](https://protectli.com/product/vp4630/) +- [Protectli TPM module](https://protectli.com/product/tpm-module/)
[Protectli VP46xx]: https://protectli.com/vault-6-port/ [MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%... diff --git a/Documentation/releases/coreboot-4.17-relnotes.md b/Documentation/releases/coreboot-4.17-relnotes.md index 2ad45ca..eb136f4 100644 --- a/Documentation/releases/coreboot-4.17-relnotes.md +++ b/Documentation/releases/coreboot-4.17-relnotes.md @@ -12,11 +12,7 @@
Major Bugfixes in this release ------------------------------ -```{toctree} -:maxdepth: 1 - -CVE-2022-29264 https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-29264 -``` +* [CVE-2022-29264](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-29264)
New Mainboards diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md index d2629b4..b7dbc5f 100644 --- a/Documentation/soc/intel/fit.md +++ b/Documentation/soc/intel/fit.md @@ -56,9 +56,5 @@
## References
-```{toctree} -:maxdepth: 1 - -Intel TXT LAB handout https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf -FIT BIOS specification https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf -``` +* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf) +* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios...) diff --git a/Documentation/soc/intel/fsp/ppi/ppi.md b/Documentation/soc/intel/fsp/ppi/ppi.md index bb14af0..6d7afb4 100644 --- a/Documentation/soc/intel/fsp/ppi/ppi.md +++ b/Documentation/soc/intel/fsp/ppi/ppi.md @@ -6,17 +6,9 @@ where FSP should be able to locate PPI, published by boot firmware and able to execute the same in FSP's context.
-```{toctree} -:maxdepth: 1 - -What is PPI https://www.intel.com/content/dam/www/public/us/en/documents/reference-guides/efi-pei-cis-v09.pdf -``` +* [What is PPI](https://www.intel.com/content/dam/www/public/us/en/documents/reference-guide...)
## List of PPI service
### Publish MP Service PPI from boot firmware (coreboot) to initialize CPU -```{toctree} -:maxdepth: 1 - -MP Service PPI <mp_service_ppi.md> -``` +- [MP Service PPI](mp_service_ppi.md) diff --git a/Documentation/technotes/console.md b/Documentation/technotes/console.md index 1b022a2..a125728 100644 --- a/Documentation/technotes/console.md +++ b/Documentation/technotes/console.md @@ -57,18 +57,10 @@
If not we can use other I2C slave devices like an Arduino or a Beagleboard. -```{toctree} -:maxdepth: 1 - -Linux I2C Slave interface https://web.archive.org/web/20220926173943/https://www.kernel.org/doc/html/latest/i2c/slave-interface.html -BeagleBone Black I2C Slave https://web.archive.org/web/20220926171211/https://forum.beagleboard.org/t/beaglebone-black-and-arduino-uno-i2c-communication-using-c/29990/8 -``` +* [Linux I2C Slave interface](https://web.archive.org/web/20220926173943/https://www.kernel.org/doc/html/l...) +* [BeagleBone Black I2C Slave](https://web.archive.org/web/20220926171211/https://forum.beagleboard.org/t/b...)
This feature was added as part of a GSoC 2022 project. Checkout the following blog posts for more details. -```{toctree} -:maxdepth: 1 - -coreboot Console via SMBus — Part I https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-38273691a8ac -coreboot Console via SMBus — Part II https://medium.com/@husnifaiz/coreboot-console-via-smbus-part-ii-bc324fdd2f24 -``` +* [coreboot Console via SMBus — Part I](https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-382736...) +* [coreboot Console via SMBus — Part II](https://medium.com/@husnifaiz/coreboot-console-via-smbus-part-ii-bc324fdd2f2...)