Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57051 )
Change subject: soc/amd/common/block/lpc,mb/google/guybrush: Use #defines for eSPI setup ......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/bootblock.c:
https://review.coreboot.org/c/coreboot/+/57051/comment/8cd08cee_4296635c PS1, Line 51: dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); : dword &= ~(LDRQ0_PD_EN | LDRQ0_EN | BIT(3)); : dword |= LDRQ0_PU_EN; : pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); : : pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0); : pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0); : : dword = pm_read32(0x90); : dword |= 1 << 16; : pm_write32(0x90, dword); : : dword = pm_read32(PM_ACPI_CONF); : dword |= 3 << 10; : pm_write32(PM_ACPI_CONF, dword);
I agree. That's part of b/183149183. […]
I already started working on that one and probably have some local changes, but it got stalled a bit on the issue with the bit names. i was asked to prioritize working on another bug yesterday