[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Use SBI msg to disable HECI1

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61456 )

Change subject: soc/intel/jasperlake: Use SBI msg to disable HECI1
......................................................................

soc/intel/jasperlake: Use SBI msg to disable HECI1

Select HECI_DISABLE_USING_SMM config for Jasper Lake to disable HECI1
device using the SBI msg in SMM.

BUG=none
TEST=None

Signed-off-by: Subrata Banik 
Change-Id: I3e8568750ec941fc8b8e7407bad027f7175953c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61456
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/jasperlake/smihandler.c
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 556b2f2..8fb0f49 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -64,7 +64,7 @@
    select UDELAY_TSC
    select UDK_202005_BINDING
    select DISPLAY_FSP_VERSION_INFO_2
-	select HECI_DISABLE_USING_SMM
+	select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT

config DCACHE_RAM_BASE
    default 0xfef00000
diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c
index 3dca4a2..f2294fe 100644
--- a/src/soc/intel/jasperlake/smihandler.c
+++ b/src/soc/intel/jasperlake/smihandler.c
@@ -16,7 +16,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
    	heci1_disable();
 }

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.