Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84213?usp=email )
Change subject: mainboard/hardkernel: Add ODROID H4+ initial support ......................................................................
mainboard/hardkernel: Add ODROID H4+ initial support
TEST=Boots to Ubuntu 23.04 from NVMe using MrChromebox UEFIPayload.
Change-Id: Iee066cb0da27e3bf7ce52fc199396185912893aa Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com --- A configs/config.hardkernel_odroid_h4plus A src/mainboard/hardkernel/Kconfig A src/mainboard/hardkernel/Kconfig.name A src/mainboard/hardkernel/odroid_h4/Kconfig A src/mainboard/hardkernel/odroid_h4/Kconfig.name A src/mainboard/hardkernel/odroid_h4/Makefile.mk A src/mainboard/hardkernel/odroid_h4/board_info.txt A src/mainboard/hardkernel/odroid_h4/bootblock.c A src/mainboard/hardkernel/odroid_h4/data.vbt A src/mainboard/hardkernel/odroid_h4/devicetree.cb A src/mainboard/hardkernel/odroid_h4/die.c A src/mainboard/hardkernel/odroid_h4/dsdt.asl A src/mainboard/hardkernel/odroid_h4/gpio.c A src/mainboard/hardkernel/odroid_h4/gpio.h A src/mainboard/hardkernel/odroid_h4/hda_verb.c A src/mainboard/hardkernel/odroid_h4/mainboard.c A src/mainboard/hardkernel/odroid_h4/romstage_fsp_params.c A src/mainboard/hardkernel/odroid_h4/vboot-rwa.fmd 18 files changed, 1,064 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/84213/1
diff --git a/configs/config.hardkernel_odroid_h4plus b/configs/config.hardkernel_odroid_h4plus new file mode 100644 index 0000000..64da3b7 --- /dev/null +++ b/configs/config.hardkernel_odroid_h4plus @@ -0,0 +1,15 @@ +CONFIG_VENDOR_HARDKERNEL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VBOOT=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_TPM2=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE" diff --git a/src/mainboard/hardkernel/Kconfig b/src/mainboard/hardkernel/Kconfig new file mode 100644 index 0000000..eff82b2 --- /dev/null +++ b/src/mainboard/hardkernel/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_HARDKERNEL + +choice + prompt "Mainboard model" + +source "src/mainboard/hardkernel/*/Kconfig.name" + +endchoice + +source "src/mainboard/hardkernel/*/Kconfig" + +config MAINBOARD_VENDOR + default "Hardkernel" + +endif # VENDOR_HARDKERNEL diff --git a/src/mainboard/hardkernel/Kconfig.name b/src/mainboard/hardkernel/Kconfig.name new file mode 100644 index 0000000..ff0f70d --- /dev/null +++ b/src/mainboard/hardkernel/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_HARDKERNEL + bool "Hardkernel" diff --git a/src/mainboard/hardkernel/odroid_h4/Kconfig b/src/mainboard/hardkernel/odroid_h4/Kconfig new file mode 100644 index 0000000..3894378 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/Kconfig @@ -0,0 +1,61 @@ +if BOARD_HARDKERNEL_ODROID_H4PLUS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_ALDERLAKE_PCH_N + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SUPERIO_ITE_IT8613E + select CRB_TPM + select DRIVERS_UART_8250IO + select FSP_TYPE_IOT + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_INTEL_PTT + select INTEL_GMA_HAVE_VBT + select USE_DDR5 + +config MAINBOARD_DIR + default "hardkernel/odroid_h4" + +config MAINBOARD_PART_NUMBER + default "ODROID-H4" + +config MAINBOARD_VENDOR + default "HARDKERNEL" + +config MAINBOARD_FAMILY + default "Default String" + +config DIMM_SPD_SIZE + default 1024 + +config UART_FOR_CONSOLE + default 0 + +config USE_PM_ACPI_TIMER + default n + +config CBFS_SIZE + default 0xa00000 + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_NO_BOARD_SUPPORT + select HAS_RECOVERY_MRC_CACHE + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config FMDFILE + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + +endif diff --git a/src/mainboard/hardkernel/odroid_h4/Kconfig.name b/src/mainboard/hardkernel/odroid_h4/Kconfig.name new file mode 100644 index 0000000..f9d3656 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HARDKERNEL_ODROID_H4PLUS + bool "ODROID H4+" diff --git a/src/mainboard/hardkernel/odroid_h4/Makefile.mk b/src/mainboard/hardkernel/odroid_h4/Makefile.mk new file mode 100644 index 0000000..f2bc230 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/Makefile.mk @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += gpio.c +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c +ramstage-y += gpio.c + +bootblock-y += die.c +romstage-y += die.c diff --git a/src/mainboard/hardkernel/odroid_h4/board_info.txt b/src/mainboard/hardkernel/odroid_h4/board_info.txt new file mode 100644 index 0000000..23c4523 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/board_info.txt @@ -0,0 +1,7 @@ +Category: sbc +Board URL: https://www.hardkernel.com/shop/odroid-h4-plus/ +ROM IC: Winbond W25Q128FW +ROM package: SOIC8-8 +ROM socketed: no +Flashrom support: yes +Release year: 2023 diff --git a/src/mainboard/hardkernel/odroid_h4/bootblock.c b/src/mainboard/hardkernel/odroid_h4/bootblock.c new file mode 100644 index 0000000..31f2897 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/bootblock.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> +#include <superio/ite/it8613e/it8613e.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +#define ITE_GPIO_BASE 0xa00 +#define ITE_GPIO_PIN(x) (1 << ((x) % 10)) +#define ITE_GPIO_SET(x) (((x) / 10) - 1) +#define ITE_GPIO_IO_ADDR(x) (ITE_GPIO_BASE + ITE_GPIO_SET(x)) + +static void ite_set_gpio_iobase(u16 iobase) +{ + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO1, iobase); + pnp_exit_conf_state(GPIO_DEV); +} + +void bootblock_mainboard_early_init(void) +{ + /* Internal VCC_OK */ + ite_reg_write(GPIO_DEV, 0x23, 0x40); + /* Pin7 as GP23 - USB2_EN */ + ite_reg_write(GPIO_DEV, 0x26, 0xfb); + /* Pin24 as GPO50 (value of 0 on bit0 is reserved, JP1 strapping)*/ + ite_reg_write(GPIO_DEV, 0x29, 0x01); + /* K8 power sequence sofyware disabled */ + ite_reg_write(GPIO_DEV, 0x2c, 0x41); + /* PCICLK 25MHz */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); + ite_kill_watchdog(GPIO_DEV); + /* GP21 - USB3_EN, VBUS power gate for the USB3.x ports */ + ite_gpio_setup(GPIO_DEV, 21, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_CONTROL_DEFAULT); + /* GP23 - USB2_EN, VBUS power gate for the USB2.x ports */ + ite_gpio_setup(GPIO_DEV, 23, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_CONTROL_DEFAULT); + + ite_set_gpio_iobase(ITE_GPIO_BASE); + /* GP21 and GP23 to low to enable USB ports VBUS */ + outb(inb(ITE_GPIO_IO_ADDR(21)) & ~ITE_GPIO_PIN(21), ITE_GPIO_IO_ADDR(21)); + outb(inb(ITE_GPIO_IO_ADDR(23)) & ~ITE_GPIO_PIN(23), ITE_GPIO_IO_ADDR(23)); + + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/hardkernel/odroid_h4/data.vbt b/src/mainboard/hardkernel/odroid_h4/data.vbt new file mode 100644 index 0000000..a3c168f --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/data.vbt Binary files differ diff --git a/src/mainboard/hardkernel/odroid_h4/devicetree.cb b/src/mainboard/hardkernel/odroid_h4/devicetree.cb new file mode 100644 index 0000000..52c0d74 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/devicetree.cb @@ -0,0 +1,223 @@ +chip soc/intel/alderlake + # FSP configuration + + register "eist_enable" = "1" + + # Sagv Configuration + register "sagv" = "SaGv_Enabled" + register "RMT" = "0" + register "enable_c6dram" = "1" + + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + register "tcc_offset" = "10" # TCC of 90C + + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x8086 0x7270 inherit + device ref igpu on + register "ddi_portA_config" = "1" # HDMI on port A + register "ddi_portB_config" = "1" # DP on port B + # Fixed DP in TCP0 + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + end + + device ref xhci on + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 3.0 front + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 3.0 front + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # EXT_HEAD1 + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # EXT_HEAD1 + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 front + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # EXT_HEAD1 + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 front + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + register "usb2_ports[10]" = "USB2_PORT_EMPTY" + register "usb2_ports[11]" = "USB2_PORT_EMPTY" + register "usb2_ports[12]" = "USB2_PORT_EMPTY" + register "usb2_ports[13]" = "USB2_PORT_EMPTY" + register "usb2_ports[14]" = "USB2_PORT_EMPTY" + register "usb2_ports[15]" = "USB2_PORT_EMPTY" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A 3.0 front + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A 3.0 front + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + register "usb3_ports[6]" = "USB3_PORT_EMPTY" + register "usb3_ports[7]" = "USB3_PORT_EMPTY" + register "usb3_ports[8]" = "USB3_PORT_EMPTY" + register "usb3_ports[9]" = "USB3_PORT_EMPTY" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 2 (USB3_LAN1)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1 (USB3_LAN1)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Port 3 (EXT_HEAD1)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Port 4 (EXT_HEAD1)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 5 (USBLAN1)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Port 6 (EXT_HEAD1)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 7 (USBLAN1)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 2))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb2_port7 on end + end + end + end + end + + device ref i2c0 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + end + device ref i2c1 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref heci1 on end + device ref sata on + register "sata_salp_support" = "1" + + register "sata_ports_enable" = "{ + [0] = 0, + [1] = 1, + }" + end + + device ref emmc on + register "emmc_enable_hs400_mode" = "true" + end + + # LAN1 Intel i226 + device ref pcie_rp3 on + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 1, + .clk_req = 1, + }" + end + # LAN2 Intel i226 + device ref pcie_rp4 on + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 2, + .clk_req = 2, + }" + end + # ASMedia PCie to 4xSATA + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 3, + .clk_req = 3, + }" + end + + # NVMe x4 link + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 0, + .clk_req = 0, + }" + end + + device ref pch_espi on + # LPC generic I/O ranges + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x000c0081" + register "gen3_dec" = "0x00fc0201" + + chip superio/ite/it8613e + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0xf1 = 0x52 # IRQ low level + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa20 + io 0x62 = 0xa10 + irq 0x70 = 0 # Don't use IRQ + irq 0xf4 = 0x20 # PSON_N is inverted SUSB_N + irq 0xfa = 0x20 # Enable WDT output through PWRGD + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0xa08 + io 0x62 = 0xa00 + end + device pnp 2e.a off end # CIR + end + end + device ref p2sb hidden end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + end + device ref hda on + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "true" + register "pch_hda_sdi_enable[0]" = "1" + end + device ref smbus on end + + chip drivers/crb + device mmio 0xfed40000 on end + end + end +end diff --git a/src/mainboard/hardkernel/odroid_h4/die.c b/src/mainboard/hardkernel/odroid_h4/die.c new file mode 100644 index 0000000..85fe229 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/die.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/gpio.h> +#include <delay.h> +#include <gpio.h> + +void die_notify(void) +{ + static uint8_t blink = 0; + + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink */ + gpio_output(GPP_B14, 0); + + while (1) { + gpio_set(GPP_B14, blink); + blink ^= 1; + mdelay(500); + } +} diff --git a/src/mainboard/hardkernel/odroid_h4/dsdt.asl b/src/mainboard/hardkernel/odroid_h4/dsdt.asl new file mode 100644 index 0000000..584f330 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/hardkernel/odroid_h4/gpio.c b/src/mainboard/hardkernel/odroid_h4/gpio.c new file mode 100644 index 0000000..7d1687c --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/gpio.c @@ -0,0 +1,453 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> + +#include "gpio.h" + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* GPP_B2 - VRALERT# */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + /* GPP_B8 - GPIO EMMC_DET# */ + PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - SATA_LED# */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF4), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_T ------- */ + + PAD_NC(GPP_T0, NONE), + PAD_NC(GPP_T1, NONE), + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + PAD_NC(GPP_T4, NONE), + PAD_NC(GPP_T5, NONE), + PAD_NC(GPP_T6, NONE), + PAD_NC(GPP_T7, NONE), + PAD_NC(GPP_T8, NONE), + PAD_NC(GPP_T9, NONE), + PAD_NC(GPP_T10, NONE), + PAD_NC(GPP_T11, NONE), + PAD_NC(GPP_T12, NONE), + PAD_NC(GPP_T13, NONE), + PAD_NC(GPP_T14, NONE), + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + /* GPP_A8 - LAN_DISABLE# */ + PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP), + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_NC(GPP_A11, NONE), + /* GPP_A12 - SATAXPCIE1 */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* GPP_A19 - DDSP_HPD1 */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + + PAD_NC(GPP_I5, NONE), + /* GPP_I7 - EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + /* GPP_I8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + /* GPP_I9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + /* GPP_I10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + /* GPP_I11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + /* GPP_I12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + /* GPP_I13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + /* GPP_I14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + /* GPP_I15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + /* GPP_I16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + /* GPP_I17 - EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + /* GPP_I18 - EMMC_RESET# */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_H ------- */ + + PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* GPP_H6 - I2C1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* GPP_H7 - I2C1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + PAD_NC(GPP_H16, NONE), + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + /* GPP_D5 - SRCCLKREQ0# to PCIE RP 9 (NVMe) */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D6 - SRCCLKREQ1# to PCIE RP 3 (LAN1) */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* GPP_D7 - SRCCLKREQ2# to PCIE RP 4 (LAN2) */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D8 - SRCCLKREQ3# presumably for PCIE RP7, but permanently grounded? */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D9, NATIVE), + PAD_NC(GPP_D10, NATIVE), + PAD_NC(GPP_D11, NATIVE), + PAD_NC(GPP_D12, NATIVE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + /* GPP_VGPIO_THC0 - GPP_VGPIO_THC0 */ + PAD_CFG_NF(GPP_VGPIO_THC0, NONE, DEEP, NF1), + /* GPP_VGPIO_THC1 - GPP_VGPIO_THC1 */ + PAD_CFG_NF(GPP_VGPIO_THC1, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + PAD_NC(GPD2, NONE), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + /* GPD8 - SUS_CLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_NC(GPD11, NONE), + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_NC(GPP_C2, NONE), + PAD_NC(GPP_C3, NONE), + PAD_NC(GPP_C4, NONE), + PAD_NC(GPP_C5, NONE), + PAD_NC(GPP_C6, NONE), + PAD_NC(GPP_C7, NONE), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + + /* GPP_L_BKLTEN - n/a */ + PAD_NC(GPP_L_BKLTEN, NONE), + /* GPP_L_BKLTCTL - n/a */ + PAD_NC(GPP_L_BKLTCTL, NONE), + /* GPP_L_VDDEN - n/a */ + PAD_NC(GPP_L_VDDEN, NONE), + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 - Reserved */ + PAD_NC(GPP_E15, NONE ), + /* GPP_E16 - Connetced to pad 67 in M.2 NVMe slot */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + PAD_NC(GPP_E17, NONE), + /* GPP_E18 - DDP1_CTRLCLK */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* GPP_E19 - DDP1_CTRLDATA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_NC(GPP_E20, NATIVE), + PAD_NC(GPP_E21, NATIVE), + /* GPP_E22 - DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), + /* GPP_E23 - DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* GPP_R4 - HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE) +}; + +const struct pad_config *board_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/hardkernel/odroid_h4/gpio.h b/src/mainboard/hardkernel/odroid_h4/gpio.h new file mode 100644 index 0000000..e2c63ae --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +const struct pad_config *board_gpio_table(size_t *num); + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/hardkernel/odroid_h4/hda_verb.c b/src/mainboard/hardkernel/odroid_h4/hda_verb.c new file mode 100644 index 0000000..86e9f29 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/hda_verb.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek ALC897 */ + 0x10ec0897, /* Vendor ID */ + 0x10ec0000, /* Subsystem ID */ + 16, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x10ec0000), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01214010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40210201), + AZALIA_PIN_CFG(0, 0x1e, 0x01441120), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + /* Alderlake-P HDMI */ + 0x8086281c, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_RESET(1), + 0x00278111, + 0x00278111, + 0x00278111, + 0x00278111, + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), + 0x00278100, + 0x00278100, + 0x00278100, + 0x00278100 +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hardkernel/odroid_h4/mainboard.c b/src/mainboard/hardkernel/odroid_h4/mainboard.c new file mode 100644 index 0000000..edbf623 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/mainboard.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/ramstage.h> +#include <soc/gpio.h> +#include <gpio.h> +#include <string.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm)); + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + + params->PcieRpEnableCpm[2] = 1; // LAN1 + params->PcieRpEnableCpm[3] = 1; // LAN2 + params->PcieRpEnableCpm[6] = 1; // ASMedia PCIe to SATA + params->PcieRpEnableCpm[8] = 1; // NVMe + + // Max payload 256B + memset(params->PcieRpMaxPayload, 1, sizeof(params->PcieRpMaxPayload)); + + // I2C + params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6 + params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7 + + params->CnviRfResetPinMux = 0; + params->CnviClkreqPinMux = 0; + + /* GPP_B8 is EMMC_DET#, active low */ + gpio_input_pullup(GPP_B8); + params->ScsEmmcEnabled = !gpio_get(GPP_B8); + + +} diff --git a/src/mainboard/hardkernel/odroid_h4/romstage_fsp_params.c b/src/mainboard/hardkernel/odroid_h4/romstage_fsp_params.c new file mode 100644 index 0000000..2fb790d --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/romstage_fsp_params.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <soc/meminit.h> +#include <soc/gpio.h> + +#include "gpio.h" + +static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + .ect = true, /* Early Command Training */ + .UserBd = BOARD_TYPE_MOBILE, + .LpDdrDqDqsReTraining = 1, +}; + +static const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x52, + }, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct pad_config *pads; + size_t num; + + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); + + pads = board_gpio_table(&num); + gpio_configure_pads(pads, num); + + memupd->FspmConfig.DmiMaxLinkSpeed = 4; +} diff --git a/src/mainboard/hardkernel/odroid_h4/vboot-rwa.fmd b/src/mainboard/hardkernel/odroid_h4/vboot-rwa.fmd new file mode 100644 index 0000000..c0956c5 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff000000 16M { + SI_ALL 6M { + SI_DESC 4K + SI_ME 0x413000 + SI_DEVICEEXT2 + } + SI_BIOS 10M { + SMMSTORE(PRESERVE) 256K + + RW_MISC 260K { + UNIFIED_MRC_CACHE(PRESERVE) { + RECOVERY_MRC_CACHE 128K + RW_MRC_CACHE 128K + } + RW_NVRAM(PRESERVE) 4K + } + + RW_SECTION_A { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + + WP_RO 5M { + RO_SECTION { + FMAP 2K + RO_FRID 0x100 + RO_FRID_PAD 0x700 + GBB 12K + COREBOOT(CBFS) + } + } + } +}