[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy/variants/nautilus: Enable AER and LTR for root port 0

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22923

Change subject: mb/google/poppy/variants/nautilus: Enable AER and LTR for root port 0
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mb/google/poppy/variants/nautilus: Enable AER and LTR for root port 0

BUG=b:65570878

Change-Id: Iadad3d2fc46cbba575a776071305925c529a6760
Signed-off-by: Furquan Shaikh 
---
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/22923/1

diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index ac3bd1d..46b0946 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -157,6 +157,10 @@
    register "PcieRpClkReqSupport[0]" = "1"
    # RP 1 uses SRCCLKREQ1#
    register "PcieRpClkReqNumber[0]" = "1"
+	# RP 1, Enable Advanced Error Reporting
+	register "PcieRpAdvancedErrorReporting[0]" = "1"
+	# RP 1, Enable Latency Tolerance Reporting Mechanism
+	register "PcieRpLtrEnable[0]" = "1"

register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
    register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port