Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59687 )
Change subject: Cezanne FSP wrapper: Sync with PI 1.0.0.5 ......................................................................
Cezanne FSP wrapper: Sync with PI 1.0.0.5
New PI 1.0.0.5 has more data in HOB of DMI, which has been uploaded to google internal repo. The dismatched size of HOB causes the wrong data tranfer. So the coreboot also need to change.
BUG=b:204732649
Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5 Signed-off-by: Zheng Bao fishbaozi@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/59687 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Rob Barnes robbarnes@google.com Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/vendorcode/amd/fsp/cezanne/dmi_info.h 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Rob Barnes: Looks good to me, approved
diff --git a/src/vendorcode/amd/fsp/cezanne/dmi_info.h b/src/vendorcode/amd/fsp/cezanne/dmi_info.h index 304f387..d2c26fa 100644 --- a/src/vendorcode/amd/fsp/cezanne/dmi_info.h +++ b/src/vendorcode/amd/fsp/cezanne/dmi_info.h @@ -227,6 +227,9 @@ OUT UINT64 VolatileSize; ///< Size of the Volatile portion of the memory device in Bytes, if any. OUT UINT64 CacheSize; ///< Size of the Cache portion of the memory device in Bytes, if any. OUT UINT64 LogicalSize; ///< Size of the Logical memory device in Bytes. + // SMBIOS 3.3 + OUT UINT32 ExtendedSpeed; ///< Extended Speed + OUT UINT32 ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed } __packed TYPE17_DMI_INFO;
/// Collection of pointers to the DMI records