[coreboot-gerrit] [M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 )

Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
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Patch Set 23:

(1 comment)

File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c:

https://review.coreboot.org/c/coreboot/+/66190/comment/799de222_bc557115 
PS20, Line 16: 	.targets = {50, 30, 30, 30, 25},
> Removed these overridden values in coreboot (with patchset#23). Below is the values configured as part of FSP,
>
> [SPEW ]  Updating Rcomp Targets:
> [SPEW ]   RcompTarget[RdOdt]: 60
> [SPEW ]   RcompTarget[WrDS]: 30
> [SPEW ]   RcompTarget[WrDSCmd]: 30
> [SPEW ]   RcompTarget[WrDSCtl]: 30
> [SPEW ]   RcompTarget[WrDSClk]: 25

thanks