[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/zork: Move PCIe GPIO config from bootblock to romstage

[Matt DeVillier (Code Review)]

Attention is currently required from: Jason Nien, Martin Roth.

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69454 )

Change subject: mb/google/zork: Move PCIe GPIO config from bootblock to romstage
......................................................................

mb/google/zork: Move PCIe GPIO config from bootblock to romstage

Aligns with how things done on newer platforms/boards (eg guybrush, skyrim)
and allows for additional GPIO config in romstage (to be implemented in
a subsquent patch). No functional impact as the GPIOs only need to be
configured prior to FSP-M.

Change-Id: I609b9a8bd78587b60c0cf1ef14feda88ad3bb4a2
Signed-off-by: Matt DeVillier 
---
M src/mainboard/google/zork/bootblock.c
M src/mainboard/google/zork/romstage.c
2 files changed, 21 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/69454/1

diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c
index 022a5e0..6009308 100644
--- a/src/mainboard/google/zork/bootblock.c
+++ b/src/mainboard/google/zork/bootblock.c
@@ -11,6 +11,4 @@

gpios = variant_bootblock_gpio_table(&num_gpios, acpi_get_sleep_type());
    gpio_configure_pads(gpios, num_gpios);
-
-	baseboard_pcie_gpio_configure();
 }
diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c
index f72789a..dc35a05 100644
--- a/src/mainboard/google/zork/romstage.c
+++ b/src/mainboard/google/zork/romstage.c
@@ -2,6 +2,7 @@

#include <baseboard/variants.h>
 #include <soc/fsp.h>
+#include <soc/platform_descriptors.h>

void __weak variant_updm_update(FSP_M_CONFIG *mcfg) {}

@@ -9,3 +10,8 @@
 {
    variant_updm_update(mcfg);
 }
+
+void mb_pre_fspm(void)
+{
+	baseboard_pcie_gpio_configure();
+}