Kevin Paul Herbert (kph@meraki.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8530
-gerrit
commit 8a7b81119db78dbfd4979c92d26f04de3aa87282 Author: Kevin Paul Herbert kph@meraki.net Date: Wed Feb 25 00:36:51 2015 -0800
x86: Fix pointer arithmetic regressions from MMIO changes
During the development of bde6d30, there were several iterations and patterns tried. An intermediate pattern was the use of u32 pointers, and division by sizeof(u32). Some of these did not get properly changed to pointer types of length 1, causing a regression in the ibexpeak SATA driver.
Other regressions of this pattern are fixed here. I audited all changes to u32 types, and the other ones are safe.
Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052 Signed-off-by: Kevin Paul Herbert kph@meraki.net --- src/soc/intel/fsp_baytrail/southcluster.c | 4 ++-- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 2 +- src/southbridge/amd/amd8111/nic.c | 2 +- src/southbridge/intel/fsp_rangeley/lpc.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 878535f..ec2f94f 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -91,8 +91,8 @@ static void sc_enable_ioapic(struct device *dev) * Set SCI IRQ to IRQ9 */ write32(ilb_base + ILB_OIC, 0x100); /* AEN */ - reg32 = read32(ilb_base + (ILB_OIC/sizeof(u32))); /* Read back per BWG */ - write32(ilb_base + (ILB_ACTL/sizeof(u32)), 0); /* ACTL bit 2:0 SCIS IRQ9 */ + reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ + write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */
*ioapic_index = 0; *ioapic_data = (1 << 25); diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 5463d2b..9deeb45 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -48,7 +48,7 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) reg32 &= ~(0xf << 28); reg32 |= (port << 28); reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(base_regs + (DEBUGPORT_MISC_CONTROL / sizeof(u32)), reg32); + write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); }
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c index 21df6c0..05ca871 100644 --- a/src/southbridge/amd/amd8111/nic.c +++ b/src/southbridge/amd/amd8111/nic.c @@ -11,7 +11,7 @@ #include "amd8111.h"
-#define CMD3 (0x54/(sizeof(u32))) +#define CMD3 0x54
typedef enum { VAL3 = (1 << 31), /* VAL bit for byte 3 */ diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 8f29670..80673a6 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -52,7 +52,7 @@ static void soc_enable_apic(struct device *dev) u32 reg32; volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f); + u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f);
/* * Enable ACPI I/O and power management.