Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41759 )
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
soc/intel/tigerlake: Add Type-C IOM base address and size macro
This adds Type-C IO Manageability engine base address and size. Tigerlake EDS(#575681) section 3.4.3 describes host bridge REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000. IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16).
BUG=:b:156016218 TEST=Built and booted on Volteer.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41759 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Rajmohan Mani rajmohan.mani@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/include/soc/iomap.h 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Rajmohan Mani: Looks good to me, but someone else must approve John Zhao: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 282092f..cd964f0 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -84,6 +84,8 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))
+#define IOM_BASE_ADDRESS 0xfbc10000 +#define IOM_BASE_SIZE 0x1600
/* * I/O port address space