Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35187 )
Change subject: [NOTFORMERGE] soc/intel exit_car.S ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35187/2/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/exit_car.S:
https://review.coreboot.org/c/coreboot/+/35187/2/src/soc/intel/common/block/... PS2, Line 48: /* Disable cache ??? */
Transactions would still hit in the cache even if cache is disabled.
Perhaps so, see comment on arch/x86/exit_car.S line 36.
There will be no CR0.CD 1->0 transition when we return to arch/x86/exit_car.S, if we skip CR0.CD 0->1 transition here. Everyone else seems to do it. I thought both those transitions have some significance wrt MTRR reproramming.
https://review.coreboot.org/c/coreboot/+/35187/2/src/soc/intel/common/block/... PS2, Line 62: /* maybe redundant ? */
Not necessarily. […]
There is invd once we return to caller, arch/x86/exit_car.S line 45. And one of these three paths for soc/intel does not have it either.