Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42667 )
Change subject: soc/intel/broadwell: Use common early SPI code ......................................................................
soc/intel/broadwell: Use common early SPI code
Also make the definition in lpc.h uppercase to avoid redefinition.
Change-Id: Ifd0e8e6d8169a762a4d17839c3fd7b7e5493a344 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/include/soc/lpc.h 2 files changed, 3 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42667/1
diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index c7b3e67..27d9a3e 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -10,18 +10,7 @@ #include <reg_script.h> #include <soc/pm.h> #include <soc/romstage.h> - -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(PCH_DEV_LPC, 0xdc, reg8); -} - +#include <southbridge/intel/common/early_spi.h>
static void map_rcba(void) { @@ -105,7 +94,7 @@ void bootblock_early_southbridge_init(void) { map_rcba(); - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); enable_port80_on_lpc(); set_spi_speed(); pch_early_lpc(); diff --git a/src/soc/intel/broadwell/include/soc/lpc.h b/src/soc/intel/broadwell/include/soc/lpc.h index ad48a12..649206a 100644 --- a/src/soc/intel/broadwell/include/soc/lpc.h +++ b/src/soc/intel/broadwell/include/soc/lpc.h @@ -17,7 +17,7 @@ #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 #define GPIOBASE 0x48 -#define BIOS_CNTL 0xdc +#define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_EN (1 << 4)