Attention is currently required from: Angel Pons, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59523 )
Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT ......................................................................
Patch Set 3:
(3 comments)
File src/northbridge/intel/sandybridge/romstage.c:
https://review.coreboot.org/c/coreboot/+/59523/comment/ce10d10e_86e62625 PS2, Line 78: #if CONFIG(INTEL_TXT)
Please don't add weak symbols. Just look at what Haswell code does. […]
What about compiling the TXT romstage part always? Then we could get rid of redundant MSR writing.
File src/northbridge/intel/sandybridge/romstage.c:
https://review.coreboot.org/c/coreboot/+/59523/comment/fcb0890c_a049f706 PS3, Line 28: #if CONFIG(INTEL_TXT)
Is this guard needed?
Actually not, we can always configure the DPR
https://review.coreboot.org/c/coreboot/+/59523/comment/6e39c371_da7ac295 PS3, Line 36: pci_write_config32(HOST_BRIDGE, DPR, dpr.raw);
Where does dpr. […]
dpr.top is updated by hardware and points to TSEG base