[coreboot-gerrit] [S] Change in coreboot[master]: sb/intel/i82870: Use register_new_ioapic()

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58407 )

Change subject: sb/intel/i82870: Use register_new_ioapic()
......................................................................

sb/intel/i82870: Use register_new_ioapic()

Commentary about mixing LAPIC IDs and IOAPIC IDs was wrong,
remove it. The only platform affected is aopen/dxplplusu with
i82801dx southbridge.

Change-Id: I1276a2050cabaaf07f740c2490d92c48bd5801fa
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58407
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/southbridge/intel/i82870/ioapic.c
1 file changed, 18 insertions(+), 24 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index 65fecd1..f6a4ac0 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -8,8 +8,6 @@
 #include <assert.h>
 #include "82870.h"

-static int num_p64h2_ioapics = 0;
-
 static void p64h2_ioapic_enable(struct device *dev)
 {
    /* We have to enable MEM and Bus Master for IOAPIC */
@@ -30,34 +28,13 @@
 static void p64h2_ioapic_init(struct device *dev)
 {
    uint32_t memoryBase;
-	int apic_index, apic_id;
-
-	apic_index = num_p64h2_ioapics;
-	num_p64h2_ioapics++;
-
-	// A note on IOAPIC addresses:
-	//  0 and 1 are used for the local APICs of the dual virtual
-	//  (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
-	//  6 and 7 are used for the local APICs of the dual virtual
-	//  (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
-	//  2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
-
-	// Map APIC index into APIC ID
-	// IDs 3, 4, 5, and 8+ are available (see above note)
-
-	if (apic_index < 3)
-		apic_id = apic_index + 3;
-	else
-		apic_id = apic_index + 5;
-
-	ASSERT(apic_id < 16);       // ID is only 4 bits

// Read the MBAR address for setting up the IOAPIC in memory space
    // NOTE: this address was assigned during enumeration of the bus

memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);

-	set_ioapic_id((void *)memoryBase, apic_id);
+	register_new_ioapic((void *)memoryBase);

// Use Processor System Bus to deliver interrupts
    ioapic_set_boot_config((void *)memoryBase, true);