Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22621
Change subject: intel/bd82x6x: Fix a small mistake in DIR_ROUTE ......................................................................
intel/bd82x6x: Fix a small mistake in DIR_ROUTE
The register is 16-bits wide. If the DIR_ROUTE call ordering was reversed the previous writes would get overwritten.
See page 407ff on the Intel C216 datasheet, which says "Size: 16bits" with "Default: 3210h" for all DnnIR registers.
This also makes sense given the register offsets: 3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W [3142h would be D30IR] 3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W 3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W 3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W 314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W 3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W [discontinuity in register addresses here] 315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W [315Eh would be D21IR] 3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W
Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de --- M src/southbridge/intel/bd82x6x/pch.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/22621/1
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 51f3b94..83d9d8d 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -418,7 +418,7 @@ #define SOFT_RESET_DATA 0x38f8
#define DIR_ROUTE(x,a,b,c,d) \ - RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR))
#define RC 0x3400 /* 32bit */