[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )

Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms
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Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43980/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43980/2//COMMIT_MSG@9 
PS2, Line 9: limitation
> limitation*s*

Done

https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 119: 	cpu_id = cpu_get_cpuid();
             : 	if (cpu_id == CPUID_TIGERLAKE_A0)
             : 		params->D3ColdEnable = 0;
             : 	else
> Depends on if we will have any variant that has some boards with pre-QS and other with QS.

If is clean to rebase CB:43621 on CB:43980 and update CB:43621 only with baseboard/devicetree.cb register "TcssD3ColdEnable" = "1". Then no need to update all those variants override.cb. CB:43980 works with all existing TGLRVP configuration as well.