Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Tim Chu.
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80100?usp=email )
Change subject: soc/intel/xeon_sp/skx/soc_util: Find devices by PCI ID ......................................................................
soc/intel/xeon_sp/skx/soc_util: Find devices by PCI ID
Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree.
Change-Id: Ie5ef78523c740f23807b3acf232f1c0e29feb4c6 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/soc_util.c 2 files changed, 31 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/80100/1
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 33b5c42..897b4d5 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -9,17 +9,15 @@ #include <hob_iiouds.h> #include <soc/pch_pci_devs.h>
-#define dump_csr(fmt, dev, reg) \ - printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \ - fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ - ((uint32_t)dev >> 12) & 0x07, \ - #reg, reg, pci_s_read_config32(dev, reg)) +#define dump_csr(dev, reg) \ + printk(BIOS_SPEW, "%s reg: %s (0x%x), data: 0x%x\n", \ + dev_path(dev), \ + #reg, reg, pci_read_config32(dev, reg))
-#define dump_csr64(fmt, dev, reg) \ - printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x%x\n", \ - fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ - ((uint32_t)dev >> 12) & 0x07, #reg, reg, \ - pci_s_read_config32(dev, reg+4), pci_s_read_config32(dev, reg)) +#define dump_csr64(dev, reg) \ + printk(BIOS_SPEW, "%s reg: %s (0x%x), data: 0x%x%x\n", \ + dev_path(dev), #reg, reg, \ + pci_read_config32(dev, reg+4), pci_read_config32(dev, reg))
#define SAD_ALL_DEV 29 #define SAD_ALL_FUNC 0 @@ -76,6 +74,8 @@ #define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 #define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31)
+#define PCU_CR2_DEVID 0x2082 + #if !defined(__SIMPLE_DEVICE__) #define _UBOX_DEV(func) pcidev_path_on_root_debug(PCI_DEVFN(UBOX_DEV, func), __func__) #else diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index d61d074..a5fd830 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -96,50 +96,48 @@ void config_reset_cpl3_csrs(void) { uint32_t data, plat_info, max_min_turbo_limit_ratio; + struct device *dev;
- for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - - /* configure PCU_CR0_FUN csrs */ - pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); - data = pci_s_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) { + data = pci_read_config32(pcu0, PCU_CR0_P_STATE_LIMITS); data |= P_STATE_LIMITS_LOCK; - pci_s_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); + pci_write_config32(pcu0, PCU_CR0_P_STATE_LIMITS, data);
- plat_info = pci_s_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); - dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); + plat_info = pci_read_config32(pcu0, PCU_CR0_PLATFORM_INFO); + dump_csr64(pcu0, PCU_CR0_PLATFORM_INFO); max_min_turbo_limit_ratio = (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT; printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n", plat_info, max_min_turbo_limit_ratio); + }
- /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - data = pci_s_read_config32(cr1_dev, PCU_CR1_SAPMCTL); + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) { + data = pci_read_config32(pcu1, PCU_CR1_SAPMCTL); /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ data &= 0x0fffffff; data |= SAPMCTL_LOCK_MASK; - pci_s_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); + pci_write_config32(pcu1, PCU_CR1_SAPMCTL, data); + }
- /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); - + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { data = PCIE_IN_PKGCSTATE_L1_MASK; - pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); + pci_write_config32(pcu2, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
data = KTI_IN_PKGCSTATE_L1_MASK; - pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); + pci_write_config32(pcu2, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
data = PROCHOT_RATIO; printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); - pci_s_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); - dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); + pci_write_config32(pcu2, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); + dump_csr(pcu2, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
- data = pci_s_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); + data = pci_read_config32(pcu2, PCU_CR2_DYNAMIC_PERF_POWER_CTL); data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; - pci_s_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); + pci_write_config32(pcu2, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); } }