[coreboot-gerrit] Change in coreboot[master]: nb/intel/ironlake/memmap.c: Use `postcar_enable_tseg_cache`

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45921 )

Change subject: nb/intel/ironlake/memmap.c: Use `postcar_enable_tseg_cache`
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Patch Set 2: Code-Review-2

On hold until the purpose of caching what is marked as TSEG is clear. This might have to do with the stage cache.