Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33397
Change subject: util/amdfwtool: Align PSP NVRAM ......................................................................
util/amdfwtool: Align PSP NVRAM
Align the PSP's NVRAM item since it's intended to be updateable in the flash device.
Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M util/amdfwtool/amdfwtool.c 1 file changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/33397/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 51e913c..f2ce34c 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -79,6 +79,7 @@ #define ALIGN(val, by) (((val) + (by) - 1) & ~((by) - 1)) #define TABLE_ALIGNMENT 0x1000U #define BLOB_ALIGNMENT 0x100U +#define ERASE_ALIGNMENT 0x1000U
#define EMBEDDED_FW_SIGNATURE 0x55aa55aa #define PSP_COOKIE 0x50535024 /* 'PSP$' */ @@ -457,6 +458,31 @@ else pspdir->entries[count].addr = 1; count++; + } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) { + if (fw_table[i].filename == NULL) + continue; + /* TODO: Add a way to reserve for NVRAM without + * requiring a filename. This isn't a feature used + * by coreboot systems, so priority is very low. + */ + ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); + bytes = copy_blob(BUFF_CURRENT(*ctx), + fw_table[i].filename, BUFF_ROOM(*ctx)); + if (bytes <= 0) { + free(ctx->rom); + exit(1); + } + + pspdir->entries[count].type = fw_table[i].type; + pspdir->entries[count].subprog = fw_table[i].subprog; + pspdir->entries[count].rsvd = 0; + pspdir->entries[count].size = (uint32_t)bytes; + pspdir->entries[count].addr = RUN_CURRENT(*ctx); + + ctx->current = ALIGN(ctx->current + bytes, + BLOB_ALIGNMENT); + ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); + count++; } else if (fw_table[i].filename != NULL) { bytes = copy_blob(BUFF_CURRENT(*ctx), fw_table[i].filename, BUFF_ROOM(*ctx));