[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/common: Add common function to disable LT memory lock

[Jérémy Compostella (Code Review)]

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71655 )

Change subject: soc/intel/common: Add common function to disable LT memory lock
......................................................................

soc/intel/common: Add common function to disable LT memory lock

Add a common function to unlock memory by setting MSR 0x2E4 to 0. If
internal chipset conditions are met, it unlocks access to the DRAM.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=romstage early graphics is operational

Change-Id: Ic666919ed51f683c9a1ef0b7ba061cd2949faf1e
Signed-off-by: Jeremy Compostella 
---
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
M src/soc/intel/common/block/include/intelblocks/msr.h
3 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/71655/1

diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 534feb1..6c59a95 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -395,6 +395,13 @@
    msr_set(MSR_LT_CONTROL, LT_CONTROL_LOCK);
 }

+void cpu_lt_unlock_memory(void)
+{
+	msr_t msrval = {0};
+
+	wrmsr(MSR_LT_UNLOCK_MEMORY, msrval);
+}
+
 int get_valid_prmrr_size(void)
 {
    msr_t msr;
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index c72e1ea..024fc0b 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -174,6 +174,9 @@
 /* Lock chipset memory registers to protect SMM */
 void cpu_lt_lock_memory(void);

+/* Disable LT memory content protection */
+void cpu_lt_unlock_memory(void);
+
 /* Get a supported PRMRR size in bytes with respect to users choice */
 int get_valid_prmrr_size(void);

diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index d4d8732..160d1e83 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -50,6 +50,7 @@
 #define  POWER_CTL_C1E_MASK		(1 << 1)
 #define MSR_PRMRR_BASE_0		0x2a0
 #define MSR_EVICT_CTL			0x2e0
+#define MSR_LT_UNLOCK_MEMORY		0x2e6
 #define MSR_LT_CONTROL			0x2e7
 #define  LT_CONTROL_LOCK		(1 << 0)
 #define MSR_SGX_OWNEREPOCH0		0x300