Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9297
-gerrit
commit eb139a3339bbe6815b4e1c739049923390135f4b Author: Kein Yuan kein.yuan@intel.com Date: Tue Feb 11 17:40:31 2014 -0800
baytrail: Fix hdmi audio choppy issue
Disable VC setting for HDA so hdmi audio choppy issue will be eliminated. Change HDA initialize steps to sync with UEFI reference code.
BUG=chrome-os-partner:25651 BRANCH=Baytrail TEST=Does not have choppy noise during video playing
Original-Signed-off-by: Kein Yuan kein.yuan@intel.com
Original-Change-Id: I45d49123d369b7d075776215e709af5801ea696d Original-Reviewed-on: https://chromium-review.googlesource.com/186024 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-by: Benson Leung bleung@chromium.org Original-Tested-by: Benson Leung bleung@chromium.org Original-Commit-Queue: Bernie Thompson bhthompson@chromium.org (cherry picked from commit 9f725a40f77cd684b2e230bd226d78d87b56e73b) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: I4fc10a161e5996e14d4823491fb62a7beff39bcc --- src/soc/intel/baytrail/hda.c | 5 ----- src/soc/intel/common/hda_verb.c | 13 +++++++++++++ 2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index 010150f..9e4140d 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -31,11 +31,6 @@ #include <baytrail/ramstage.h>
static const struct reg_script init_ops[] = { - /* Set up VC0 and VC1. */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x24, 0x80000019), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x28, 0x81000022), - /* Enable VCi */ - REG_PCI_WRITE32(0x120, 0x81000022), /* Enable no snoop traffic. */ REG_PCI_OR16(0x78, 1 << 11), /* Configure HDMI codec connection. */ diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index bd61cee..2523b41 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -70,6 +70,19 @@ int hda_codec_detect(u8 *base) /* Write back the value once reset bit is set. */ write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
+ /* Clear the "State Change Status Register" STATESTS bits + * for each of the "SDIN Stat Change Status Flag" + */ + write8(base + HDA_STATESTS_REG, 0xf); + + /* Turn off the link and poll RESET# bit until it reads back as 0 */ + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0) + goto no_codec; + + /* Turn on the link and poll RESET# bit until it reads back as 1 */ + if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + goto no_codec; + /* Read in Codec location (BAR + 0xe)[2..0]*/ reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f;