Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu.
Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83538?usp=email )
Change subject: soc/intel/xeon_sp: Reserve FSP MMIO high window ......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1: Some critical log diffs:
1. The MMIO window will be added along with assign_resources
[0m[INFO ] === Resource allocator: DOMAIN: 00010dff - resource allocation complete ===[0m [0m[SPEW ] Root Device assign_resources, segment group 0 bus 0[0m [0m[SPEW ] DOMAIN: 00000000 assign_resources, segment group 0 bus 0[0m [0m[SPEW ] dev: PCI: 00:00:00.0, index: 0xc, base: 0x200000000000, size: 0x14000000000[0m
[0m[SPEW ] Show resources in subtree (Root Device)...After assigning values.[0m [0m[DEBUG] Root Device child on link 0 CPU_CLUSTER: 0[0m [0m[DEBUG] CPU_CLUSTER: 0[0m [0m[DEBUG] DOMAIN: 00000000 child on link 0 PCI: 00:00:00.0[0m [0m[SPEW ] DOMAIN: 00000000 resource base 0 size 1000 align 0 gran 0 limit fff flags 40040100 index 0[0m [0m[SPEW ] DOMAIN: 00000000 resource base 1000 size 0 align 0 gran 0 limit 3fff flags 40080100 index 1[0m [0m[SPEW ] DOMAIN: 00000000 resource base 90040000 size 0 align 0 gran 0 limit 957fffff flags 40080200 index 2[0m [0m[SPEW ] DOMAIN: 00000000 resource base 200000000000 size 0 align 0 gran 0 limit 200fffffffff flags 40080200 index 3[0m [0m[SPEW ] DOMAIN: 00000000 resource base 957fd000 size 3000 align 0 gran 0 limit 0 flags f0000200 index 4[0m [0m[DEBUG] PCI: 00:00:00.0[0m [0m[SPEW ] PCI: 00:00:00.0 resource base 957fc000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 180[0m [0m[SPEW ] PCI: 00:00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0[0m [0m[SPEW ] PCI: 00:00:00.0 resource base 100000 size 636fffff align 0 gran 0 limit 0 flags e0004200 index 1[0m [0m[SPEW ] PCI: 00:00:00.0 resource base 637fffff size 14000001 align 0 gran 0 limit 0 flags e0004200 index 2[0m [0m[SPEW ] PCI: 00:00:00.0 resource base 78000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 3[0m [0m[SPEW ] PCI: 00:00:00.0 resource base 77800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 5[0m [0m[SPEW ] PCI: 00:00:00.0 resource base 78000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 6[0m [0m[SPEW ] PCI: 00:00:00.0 resource base 100000000 size 1f80000000 align 0 gran 0 limit 0 flags e0004200 index 8[0m [0m[SPEW ] PCI: 00:00:00.0 resource base 80000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 9[0m [0m[SPEW ] PCI: 00:00:00.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a[0m [0m[SPEW ] PCI: 00:00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index b[0m [0m[SPEW ] PCI: 00:00:00.0 resource base 200000000000 size 14000000000 align 0 gran 0 limit 0 flags e0000200 index c[0m
2. MTRR assignment will be improved.
After [0m[DEBUG] MTRR: Physical address space:[0m [0m[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6[0m [0m[DEBUG] 0x00000000000a0000 - 0x00000000000fffff size 0x00060000 type 0[0m [0m[DEBUG] 0x0000000000100000 - 0x000000007fffffff size 0x7ff00000 type 6[0m [0m[DEBUG] 0x0000000080000000 - 0x00000000ffffffff size 0x80000000 type 0[0m [0m[DEBUG] 0x0000000100000000 - 0x000000207fffffff size 0x1f80000000 type 6[0m [0m[DEBUG] 0x0000200000000000 - 0x0000213fffffffff size 0x14000000000 type 0[0m
Before [0m[DEBUG] MTRR: Physical address space:[0m [0m[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6[0m [0m[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0[0m [0m[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6[0m [0m[DEBUG] 0x0000000080000000 - 0x00000000ffffffff size 0x80000000 type 0[0m [0m[DEBUG] 0x0000000100000000 - 0x000000207fffffff size 0x1f80000000 type 6[0m [0m[DEBUG] 0x0000200ffffa2000 - 0x0000200fffffffff size 0x0005e000 type 0[0m [0m[DEBUG] 0x0000201ffffe0000 - 0x0000201fffffffff size 0x00020000 type 0[0m [0m[DEBUG] 0x0000202ffffe0000 - 0x0000202fffffffff size 0x00020000 type 0[0m [0m[DEBUG] 0x0000203ffffe0000 - 0x0000203fffffffff size 0x00020000 type 0[0m [0m[DEBUG] 0x0000204ffff80000 - 0x0000204fffffffff size 0x00080000 type 0[0m [0m[DEBUG] 0x0000205ffff80000 - 0x0000205fffffffff size 0x00080000 type 0[0m [0m[DEBUG] 0x0000206ffffa0000 - 0x0000206fffffffff size 0x00060000 type 0[0m [0m[DEBUG] 0x0000207ffffa0000 - 0x0000207fffffffff size 0x00060000 type 0[0m [0m[DEBUG] 0x0000208ffffa0000 - 0x0000208fffffffff size 0x00060000 type 0[0m [0m[DEBUG] 0x0000209ffffa0000 - 0x0000209fffffffff size 0x00060000 type 0[0m [0m[DEBUG] 0x000020bffffe0000 - 0x000020bfffffffff size 0x00020000 type 0[0m [0m[DEBUG] 0x000020cffffe0000 - 0x000020cfffffffff size 0x00020000 type 0[0m [0m[DEBUG] 0x000020dffffe0000 - 0x000020dfffffffff size 0x00020000 type 0[0m [0m[DEBUG] 0x000020effff80000 - 0x000020efffffffff size 0x00080000 type 0[0m [0m[DEBUG] 0x000020fffff80000 - 0x000020ffffffffff size 0x00080000 type 0[0m [0m[DEBUG] 0x0000210ffffa0000 - 0x0000210fffffffff size 0x00060000 type 0[0m [0m[DEBUG] 0x0000211ffffa0000 - 0x0000211fffffffff size 0x00060000 type 0[0m [0m[DEBUG] 0x0000212ffffa0000 - 0x0000212fffffffff size 0x00060000 type 0[0m [0m[DEBUG] 0x0000213ffffa0000 - 0x0000213fffffffff size 0x00060000 type 0[0m