Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56919 )
Change subject: soc/amd/common: Skip psp_verstage on S0i3 resume ......................................................................
soc/amd/common: Skip psp_verstage on S0i3 resume
PSP_Verstage will take almost the entire time to run that is allotted to S0i3 resume. Since coreboot isn't running, the PSP needs to handle any security requirements. The long- term plan is that the PSP won't even load psp_verstage on S0i3 resume, but when it is loaded, this makes sure we exit immediately
BUG=b:177064859 TEST=Verify that PSP_verstage doesn't run on S0i3 resume
Signed-off-by: Martin Roth martinroth@chromium.org Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56919 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/common/psp_verstage/psp_verstage.c 1 file changed, 10 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 5c59c4f..d223c94 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -200,6 +200,16 @@ { uint32_t retval; struct vb2_context *ctx = NULL; + uint32_t bootmode = 0; + + /* + * Currently, we want to skip running verstage on all S0i3 resumes. This relies + * on an assumption that the PSP will be checksumming all of its components. + * TODO(b/196400450): Remove when PSP no longer loads verstage on S0i3 resume. + */ + svc_get_boot_mode(&bootmode); + if (bootmode == PSP_BOOT_MODE_S0i3_RESUME) + svc_exit(0);
/* * Do not use printk() before console_init()