Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35471 )
Change subject: soc/mediatek/mt8183: Refactor DRAM init by bit fields API ......................................................................
Patch Set 8:
(3 comments)
still WIP.
I plan to apply more registers before merging this.
https://review.coreboot.org/c/coreboot/+/35471/7/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/35471/7/src/soc/mediatek/mt8183/dra... PS7, Line 108: CKECTRL_CKEFIXON, cke_on,
nit: indentation for many of these is misaligned
Done
https://review.coreboot.org/c/coreboot/+/35471/7/src/soc/mediatek/mt8183/dra... PS7, Line 758: dramc_rx_dqs_isi_pulse_cg_switch(chn, false);
Why this change?
seems like some unexpected change due to rebase. solved.
https://review.coreboot.org/c/coreboot/+/35471/7/src/soc/mediatek/mt8183/inc... File src/soc/mediatek/mt8183/include/soc/dramc_register.h:
https://review.coreboot.org/c/coreboot/+/35471/7/src/soc/mediatek/mt8183/inc... PS7, Line 654: DEFINE_BITFIELD(REFCTRL0_REFDIS, 29, 29);
nit: maybe we should add a DEFINE_BIT(REFCTRL0_REFDIS, 29) that's just a shorthand for single-bit fi […]
Done