[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Enable rom cache on all CPU threads

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63486 )

Change subject: soc/intel/common: Enable rom cache on all CPU threads
......................................................................

soc/intel/common: Enable rom cache on all CPU threads

In the previous implementation, it asks all CPUs/threads to run
_x86_setup_mtrrs and BSP to run post_cpus_add_romcache.
However the BSP doesn't wait all threads to finish _x86_setup_mtrrs
and run post_cpus_add_romcache immediately. It causes a race condition
that other thread in same core could finish _x86_setup_mtrrs later
than post_cpus_add_romcache run by BSP.

MTRR is a core level MSR, so settings in post_cpus_add_romcache
could be overriden unexpectedly by other thread in the same core.
Ex: Core0, thread 1 finishes _x86_setup_mtrrs later than
post_cpus_add_romcache run by bsp Core0 thread 0.

Instead of using different MTRRs settings on BSP/APs and cause race
conditionm, this patch asks all cpu/threads to run
post_cpus_add_romcache, so that MTRRs on all cores are aligned.

This patch also calls need_restore_mtrr to
set put_back_original_solution in order to restor mtrr later in
remove_temp_solution.

BUG=b:225766934
TEST=Tested on gimble and found rom cache is set properly right before
     payload lzma decompress and restored to original mtrr in the end
     of coreboot

Change-Id: I1d7ffc6e5f5ec49abf848d3cd9f0435c93f834dc
Signed-off-by: Kane Chen 
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 6 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/63486/1

diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 823f23e..8c18840 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -152,7 +152,6 @@

init_cpus();
 }
-
 static void post_cpus_add_romcache(void)
 {
    if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED))
@@ -164,6 +163,7 @@
 static void wrapper_x86_setup_mtrrs(void *unused)
 {
    x86_setup_mtrrs_with_detect();
+	post_cpus_add_romcache();
 }

/* Ensure to re-program all MTRRs based on DRAM resource settings */
@@ -172,7 +172,11 @@
    if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS)
    	printk(BIOS_ERR, "MTRR programming failure\n");

-	post_cpus_add_romcache();
+	/* Inside wrapper_x86_setup_mtrrs, it will cache spi address.
+	 * So we need to restore mtrr later in remove_temp_solution.
+	 */
+	need_restore_mtrr();
+
    x86_mtrr_check();
 }