Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76196?usp=email )
Change subject: cpu/x86: Add some notes about XAPIC/X2APIC ......................................................................
cpu/x86: Add some notes about XAPIC/X2APIC
At the time of writing SMM runtime does not make register accesses to LAPIC registers, but such breakage has been reported.
S3 resume failure, where OS switched back from X2APIC to XAPIC mode, can be reproduced with a sandybridge SKU that has VT-d disabled.
Change-Id: I300ba87c3d8fde548dbaf95703bd7e2fe54cff57 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/x86/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/76196/1
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 1e1b2ac..4e17690 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -50,16 +50,26 @@ config XAPIC_ONLY prompt "Set XAPIC mode" bool + help + coreboot and SMM runtime only use XAPIC mode. + FIXME: DMAR should have X2APIC optout bit set.
config X2APIC_ONLY prompt "Set X2APIC mode" bool depends on PARALLEL_MP + help + coreboot and SMM runtime only use X2APIC mode. + Note: OS switches back to XAPIC mode if VT-d is disabled. + FIXME: S3 resume (and SMM runtime) will break if OS makes the switch.
config X2APIC_RUNTIME prompt "Support both XAPIC and X2APIC" bool depends on PARALLEL_MP + help + The switch to X2APIC mode happens early in ramstage. SMM runtime can + support either mode in case the OS switches back to XAPIC.
config X2APIC_LATE_WORKAROUND prompt "Use XAPIC for AP bringup, then change to X2APIC"