Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44454 )
Change subject: mb/google/puff: Implement cse_board_reset() strong symbol ......................................................................
mb/google/puff: Implement cse_board_reset() strong symbol
Since Puff uses CSE Lite SKU that supports in-field CSME updates an additional reset is triggered when jmp from RO to RW during boot. However this reset is not detected by the cr50 running older firmware because the strapping configuration for EFS2 uses PLT_RST_L to assert to cr50 that a AP reset occured. However, the older cr50 firmware version of 0.0.22 only monitors AP resets via SYS_RESET_L and hence never detects the reset.
To mitigate the issue above a modified reset sequence is required to be performed to signal the reset occured and hence a board-specific cse_board_reset() strong symbol is provided to modify the flow accordingly.
N.B, $(CONFIG_BOARD_GOOGLE_BASEBOARD_PUFF) += mainboard.c and so Hatch is un-impacted by this.
BUG=b:162290856 BRANCH=puff TEST=none
Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/variants/baseboard/mainboard.c 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/44454/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index 537e3df..0538d22 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -8,6 +8,8 @@ #include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> +#include <halt.h> +#include <intelblocks/cse.h> #include <intelblocks/power_limit.h> #include <soc/pci_devs.h> #include <timer.h> @@ -147,6 +149,13 @@ conf->tdp_psyspl2 = psyspl2; }
+void cse_board_reset(void) +{ + /* TODO: Check TPM firmware version before initiating AP reset. */ + if (!google_chromeec_ap_reset()) + halt(); +} + void variant_ramstage_init(void) { static const long display_timeout_ms = 3000;