Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13720
-gerrit
commit e59bdc655da5c74694b01e9e2d40e9df7c5d4c91 Author: Lee Leahy leroy.p.leahy@intel.com Date: Sun Feb 14 15:18:14 2016 -0800
mainboard/intel/galileo: Disable the remaining PCI devices
Add additional lines to the devicetree.cb file to disable the PCI devices in the Quark SoC.
Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * Devices show up as disabled in BS_DEV_ENUMERATE state or ramstage
Change-Id: I1edbbcb88cef29ce972ef054c82e37bf07c3761d Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/mainboard/intel/galileo/devicetree.cb | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index ab4f246..27120e6 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -19,6 +19,19 @@ chip soc/intel/quark device domain 0 on # EDS Table 3 device pci 00.0 on end # 8086 0958 - Host Bridge + device pci 14.0 off end + device pci 14.1 off end + device pci 14.2 off end + device pci 14.3 off end + device pci 14.4 off end + device pci 14.5 off end + device pci 14.6 off end + device pci 14.7 off end + device pci 15.0 off end + device pci 15.1 off end + device pci 15.2 off end + device pci 17.0 off end + device pci 17.1 off end device pci 1f.0 on end # 8086 095e - Legacy Bridge end end