Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80171?usp=email )
Change subject: mb/ocp: Drop tiogapass ......................................................................
mb/ocp: Drop tiogapass
The platform code depends on unreleased binary files and uses incomplete public header files. In order to reduce maintainance burden for the Xeon-SP platforms drop this old code.
Change-Id: I838b9ea3955d31ea393494c2e726845fe234ef3a Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- D src/mainboard/ocp/tiogapass/Kconfig D src/mainboard/ocp/tiogapass/Kconfig.name D src/mainboard/ocp/tiogapass/Makefile.inc D src/mainboard/ocp/tiogapass/acpi/platform.asl D src/mainboard/ocp/tiogapass/acpi_tables.c D src/mainboard/ocp/tiogapass/board.fmd D src/mainboard/ocp/tiogapass/board_info.txt D src/mainboard/ocp/tiogapass/bootblock.c D src/mainboard/ocp/tiogapass/console.c D src/mainboard/ocp/tiogapass/devicetree.cb D src/mainboard/ocp/tiogapass/dsdt.asl D src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h D src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h D src/mainboard/ocp/tiogapass/ipmi.c D src/mainboard/ocp/tiogapass/ipmi.h D src/mainboard/ocp/tiogapass/ramstage.c D src/mainboard/ocp/tiogapass/romstage.c D src/mainboard/ocp/tiogapass/vpd.h 18 files changed, 0 insertions(+), 1,552 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/80171/1
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig deleted file mode 100644 index 886743c..0000000 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -if BOARD_OCP_TIOGAPASS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_32768 - select HAVE_ACPI_TABLES - select IPMI_KCS - select IPMI_KCS_ROMSTAGE - select IPMI_OCP - select MAINBOARD_USES_FSP2_0 - select OCP_DMI - select SOC_INTEL_SKYLAKE_SP - select SUPERIO_ASPEED_AST2400 - select UART_OVERRIDE_BAUDRATE - select VPD - -config MAINBOARD_DIR - default "ocp/tiogapass" - -config MAINBOARD_PART_NUMBER - default "TiogaPass" - -config MAINBOARD_FAMILY - string - default "TiogaPass" - -config FMDFILE - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" - -config UART_FOR_CONSOLE - int - default 1 - -config TTYS0_BAUD - default 57600 - -endif # BOARD_OCP_TIOGAPASS diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name deleted file mode 100644 index e1bf821..0000000 --- a/src/mainboard/ocp/tiogapass/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_OCP_TIOGAPASS - bool "TiogaPass" diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc deleted file mode 100644 index bcf0e6c..0000000 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -bootblock-y += bootblock.c -romstage-y += ipmi.c -ramstage-y += ramstage.c ipmi.c - -all-y += console.c - -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl deleted file mode 100644 index 1899de1..0000000 --- a/src/mainboard/ocp/tiogapass/acpi/platform.asl +++ /dev/null @@ -1,327 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* Enable ACPI _SWS methods */ -#include <soc/intel/common/acpi/acpi_wake_source.asl> - -Name (_S0, Package (0x04) // mandatory system state -{ - 0x00, 0x00, 0x00, 0x00 -}) - -Name (_S5, Package (0x04) // mandatory system state -{ - 0x07, 0x00, 0x00, 0x00 -}) - -/* The APM port can be used for generating software SMIs */ -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -#include <arch/x86/acpi/post.asl> - -OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400) -Field (PSYS, ByteAcc, NoLock, Preserve) -{ - PLAT, 32, // Platform ID - - // IOAPIC - APC0, 1, // PCH IOAPIC Enable - AP00, 1, // PC00 IOAPIC Enable - AP01, 1, // PC01 IOAPIC Enable - AP02, 1, // PC02 IOAPIC Enable - AP03, 1, // PC03 IOAPIC Enable - AP04, 1, // PC04 IOAPIC Enable - AP05, 1, // PC05 IOAPIC Enable - AP06, 1, // PC06 IOAPIC Enable - AP07, 1, // PC07 IOAPIC Enable - AP08, 1, // PC08 IOAPIC Enable - AP09, 1, // PC09 IOAPIC Enable - AP10, 1, // PC10 IOAPIC Enable - AP11, 1, // PC11 IOAPIC Enable - AP12, 1, // PC12 IOAPIC Enable - AP13, 1, // PC13 IOAPIC Enable - AP14, 1, // PC14 IOAPIC Enable - AP15, 1, // PC15 IOAPIC Enable - AP16, 1, // PC16 IOAPIC Enable - AP17, 1, // PC17 IOAPIC Enable - AP18, 1, // PC18 IOAPIC Enable - AP19, 1, // PC19 IOAPIC Enable - AP20, 1, // PC20 IOAPIC Enable - AP21, 1, // PC21 IOAPIC Enable - AP22, 1, // PC22 IOAPIC Enable - AP23, 1, // PC23 IOAPIC Enable - RESA, 7, - SKOV, 1, // Override Socket APIC Id - RES0, 7, - - // Power Management - TPME, 1, - CSEN, 1, - C3EN, 1, - C6EN, 1, - C7EN, 1, - MWOS, 1, - PSEN, 1, - EMCA, 1, - HWAL, 2, - KPRS, 1, - MPRS, 1, - TSEN, 1, - FGTS, 1, - OSCX, 1, - RESX, 1, - - // RAS - CPHP, 8, - IIOP, 8, - IIOH, 64, - PRBM, 32, - P0ID, 32, - P1ID, 32, - P2ID, 32, - P3ID, 32, - P4ID, 32, - P5ID, 32, - P6ID, 32, - P7ID, 32, - P0BM, 64, - P1BM, 64, - P2BM, 64, - P3BM, 64, - P4BM, 64, - P5BM, 64, - P6BM, 64, - P7BM, 64, - MEBM, 16, - MEBC, 16, - CFMM, 32, - TSSY, 32, // TODO: This is TSSZ in system booted from production FW - M0BS, 64, - M1BS, 64, - M2BS, 64, - M3BS, 64, - M4BS, 64, - M5BS, 64, - M6BS, 64, - M7BS, 64, - M0RN, 64, - M1RN, 64, - M2RN, 64, - M3RN, 64, - M4RN, 64, - M5RN, 64, - M6RN, 64, - M7RN, 64, - SMI0, 32, - SMI1, 32, - SMI2, 32, - SMI3, 32, - SCI0, 32, - SCI1, 32, - SCI2, 32, - SCI3, 32, - MADD, 64, - CUU0, 128, - CUU1, 128, - CUU2, 128, - CUU3, 128, - CUU4, 128, - CUU5, 128, - CUU6, 128, - CUU7, 128, - CPSP, 8, - ME00, 128, - ME01, 128, - ME10, 128, - ME11, 128, - ME20, 128, - ME21, 128, - ME30, 128, - ME31, 128, - ME40, 128, - ME41, 128, - ME50, 128, - ME51, 128, - ME60, 128, - ME61, 128, - ME70, 128, - ME71, 128, - MESP, 16, - LDIR, 64, - PRID, 32, - AHPE, 8, - - // VTD - DHRD, 192, - ATSR, 192, - RHSA, 192, - - // SR-IOV - WSIC, 8, - WSIS, 16, - WSIB, 8, - WSID, 8, - WSIF, 8, - WSTS, 8, - WHEA, 8, - - // BIOS Guard - BGMA, 64, - BGMS, 8, - BGIO, 16, - BGIL, 8, - CNBS, 8, - - // USB3 - XHMD, 8, - SBV1, 8, - SBV2, 8, - - // HWPM - HWEN, 2, - ACEN, 1, - HWPI, 1, - RES1, 4, - - // IIO - BB00, 8, - BB01, 8, - BB02, 8, - BB03, 8, - BB04, 8, - BB05, 8, - BB06, 8, - BB07, 8, - BB08, 8, - BB09, 8, - BB10, 8, - BB11, 8, - BB12, 8, - BB13, 8, - BB14, 8, - BB15, 8, - BB16, 8, - BB17, 8, - BB18, 8, - BB19, 8, - BB20, 8, - BB21, 8, - BB22, 8, - BB23, 8, - BB24, 8, - BB25, 8, - BB26, 8, - BB27, 8, - BB28, 8, - BB29, 8, - BB30, 8, - BB31, 8, - BB32, 8, - BB33, 8, - BB34, 8, - BB35, 8, - BB36, 8, - BB37, 8, - BB38, 8, - BB39, 8, - BB40, 8, - BB41, 8, - BB42, 8, - BB43, 8, - BB44, 8, - BB45, 8, - BB46, 8, - BB47, 8, - SGEN, 8, - SG00, 8, - SG01, 8, - SG02, 8, - SG03, 8, - SG04, 8, - SG05, 8, - SG06, 8, - SG07, 8, - - // Performance - CLOD, 8, - - // XTU - XTUB, 32, - XTUS, 32, - XMBA, 32, - DDRF, 8, - RT3S, 8, - RTP0, 8, - RTP3, 8, - - // FPGA - FBB0, 8, - FBB1, 8, - FBB2, 8, - FBB3, 8, - FBB4, 8, - FBB5, 8, - FBB6, 8, - FBB7, 8, - FBL0, 8, - FBL1, 8, - FBL2, 8, - FBL3, 8, - FBL4, 8, - FBL5, 8, - FBL6, 8, - FBL7, 8, - P0FB, 8, - P1FB, 8, - P2FB, 8, - P3FB, 8, - P4FB, 8, - P5FB, 8, - P6FB, 8, - P7FB, 8, - FMB0, 32, - FMB1, 32, - FMB2, 32, - FMB3, 32, - FMB4, 32, - FMB5, 32, - FMB6, 32, - FMB7, 32, - FML0, 32, - FML1, 32, - FML2, 32, - FML3, 32, - FML4, 32, - FML5, 32, - FML6, 32, - FML7, 32, - FKPB, 32, - FKB0, 8, - FKB1, 8, - FKB2, 8, - FKB3, 8, - FKB4, 8, - FKB5, 8, - FKB6, 8, - FKB7, 8 -} - -/* - * The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method (_PTS, 1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method (_WAK, 1) -{ - Return (Package (){ 0, 0 }) -} diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c deleted file mode 100644 index b6e3846..0000000 --- a/src/mainboard/ocp/tiogapass/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t *fadt) -{ - fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; -} diff --git a/src/mainboard/ocp/tiogapass/board.fmd b/src/mainboard/ocp/tiogapass/board.fmd deleted file mode 100644 index 2ecce06..0000000 --- a/src/mainboard/ocp/tiogapass/board.fmd +++ /dev/null @@ -1,19 +0,0 @@ -FLASH 32M { - SI_ALL@0x0 0xa36000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0xa23000 - PLATFORM_DATA@0xa26000 0x10000 - } - SI_BIOS@0x1000000 0x1000000 { - MISC_RW@0x0 0x10000 { - RW_VPD(PRESERVE)@0x0 0x4000 - } - WP_RO@0x10000 0xff0000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0xfec000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x800 0xfeb800 - } - } - } -} diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt deleted file mode 100644 index e86f78f..0000000 --- a/src/mainboard/ocp/tiogapass/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: TiogaPass -Category: server -ROM protocol: SPI -ROM socketed: yes -Release year: 2018 diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c deleted file mode 100644 index 6bcbfcc..0000000 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <intelblocks/pcr.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> -#include <superio/aspeed/ast2400/ast2400.h> -#include <superio/aspeed/common/aspeed.h> -#include <tp_pch_gpio.h> - -/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 -#define ASPEED_CONFIG_INDEX 0x2E -#define ASPEED_CONFIG_DATA 0x2F - -static void enable_espi_lpc_io_windows(void) -{ - /* - * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, - * one is connected to debug header (SUART1) and another is used as SOL (SUART2). - * For that end it is wired into BMC virtual port. - */ - - /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ - pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); - /* LPC I/O enable: com1 and com2 */ - pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); - - /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ - pci_s_write_config32(PCH_DEV_LPC, 0x80, - (1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4)); -} - -static uint8_t com_to_ast_sio(uint8_t com) -{ - switch (com) { - case 0: - return AST2400_SUART1; - case 1: - return AST2400_SUART2; - case 2: - return AST2400_SUART3; - case 4: - return AST2400_SUART4; - default: - return AST2400_SUART1; - } -} - -void bootblock_mainboard_early_init(void) -{ - /* pre-configure Lewisburg PCH GPIO pads */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - - /* Open IO windows */ - enable_espi_lpc_io_windows(); - - /* Configure appropriate physical port of SuperIO chip off BMC */ - const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX, - com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); - aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); - - /* Port 80h direct to GPIO for LED display */ - const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO); - aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH); - - /* Enable UART function pin */ - aspeed_enable_uart_pin(serial_dev); -} diff --git a/src/mainboard/ocp/tiogapass/console.c b/src/mainboard/ocp/tiogapass/console.c deleted file mode 100644 index 2cbeb3d..0000000 --- a/src/mainboard/ocp/tiogapass/console.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/uart.h> - -unsigned int get_uart_baudrate(void) -{ - /* SOL console baud rate. */ - return 57600; -} diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb deleted file mode 100644 index fbf0662..0000000 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ /dev/null @@ -1,90 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -chip soc/intel/xeon_sp/skx - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # configure device interrupt routing - register "ir00_routing" = "0x3210" # IR00, Dev31 - register "ir01_routing" = "0x3210" # IR01, Dev30 - register "ir02_routing" = "0x3210" # IR02, Dev29 - register "ir03_routing" = "0x3210" # IR03, Dev28 - register "ir04_routing" = "0x3210" # IR04, Dev27 - - # configure interrupt polarity control - register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow - register "ipc1" = "0x00000000" # IPC1 - register "ipc2" = "0x00000000" # IPC2 - register "ipc3" = "0x00000000" # IPC3 - - # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs - # FB production turbo_ratio_limit is 0x1f1f1f2022222325 - register "turbo_ratio_limit" = "0x1b1b1b1d20222325" - # FB production turbo_ratio_limit_cores is 0x1c1812100c080402 - register "turbo_ratio_limit_cores" = "0x1c1814100c080402" - - # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL - register "pstate_req_ratio" = "0xa" - - # configure VTD - register "vtd_support" = "1" - register "coherency_support" = "1" - register "ats_support" = "1" - - register "gen2_dec" = "0x000c0ca1" # IPMI KCS - - device cpu_cluster 0 on end - - device domain 0 on - device gpio 0 alias pch_gpio on end - device pci 00.0 on end # Host bridge - device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers - device pci 05.2 on end # Intel Corporation Device 2025 - device pci 05.4 on end # Intel Corporation Device 2026 - device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers - device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers - device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers - device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0 - device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1 - device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode] - device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller - device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1 - device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2 - device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3 - device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode] - device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1 - device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5 - device pci 1f.0 on - chip drivers/ipmi # BMC KCS - device pnp ca2.0 on end - use pch_gpio as gpio_dev - register "bmc_i2c_address" = "0x20" - register "bmc_boot_timeout" = "90" - register "post_complete_gpio" = "GPP_B20" - register "post_complete_invert" = "1" - end - chip drivers/ipmi/ocp # OCP specific IPMI porting - device pnp ca2.1 on end - end - end # Intel Corporation C621 Series Chipset LPC/eSPI Controller - device pci 1f.1 hidden end # p2sb - device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller - device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus - device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller - end -end diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl deleted file mode 100644 index 06145c4..0000000 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - - -#include <acpi/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 -) -{ - #include <acpi/dsdt_top.asl> - #include "acpi/platform.asl" - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> - #include <cpu/intel/common/acpi/cpu.asl> - #include <soc/intel/xeon_sp/acpi/uncore.asl> - Scope (_SB.PC00) - { - #include <soc/intel/xeon_sp/acpi/pch.asl> - } -} diff --git a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h deleted file mode 100644 index b66d773..0000000 --- a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SKXSP_TP_IIO_H_ -#define _SKXSP_TP_IIO_H_ - -#include <FspmUpd.h> -#include <soc/pci_devs.h> - -enum tp_iio_bifur_table_index { - Skt0_Iou0 = 0, - Skt0_Iou1, - Skt0_Iou2, - Skt0_Mcp0, - Skt0_Mcp1, - Skt1_Iou0, - Skt1_Iou1, - Skt1_Iou2, - Skt1_Mcp0, - Skt1_Mcp1 -}; - -/* - * Standard Tioga Pass Iio Bifurcation Table - * This is SS 2x16 config. As documented in OCP TP spec, there are - * 3 configs. SS 2x16 is the most common. - * TODO: figure out config through board SKU ID and through PCIe - * config GPIO setting (SLT_CFG0 / SLT_CFG1). - */ -static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = { - { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */ - { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */ - { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */ - { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ - { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ - { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */ - { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */ - { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */ - { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ - { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ -}; - -#define CFG_UPD_PORT(port, hide) \ - { \ - .PortIndex = port, \ - .HidePort = hide, \ - .DeEmphasis = 0x00, \ - .PortLinkSpeed = PcieAuto, \ - .MaxPayload = 0x00, \ - .DfxDnTxPreset = 0xFF, \ - .DfxRxPreset = 0xFF, \ - .DfxUpTxPreset = 0xFF, \ - .Sris = 0x00, \ - .PcieCommonClock = 0x00, \ - .NtbPpd = NTB_PORT_TRANSPARENT, \ - .NtbSplitBar = 0x00, \ - .NtbBarSizePBar23 = 0x16, \ - .NtbBarSizePBar4 = 0x16, \ - .NtbBarSizePBar5 = 0x16, \ - .NtbBarSizePBar45 = 0x16, \ - .NtbBarSizeSBar23 = 0x16, \ - .NtbBarSizeSBar4 = 0x16, \ - .NtbBarSizeSBar5 = 0x16, \ - .NtbBarSizeSBar45 = 0x16, \ - .NtbSBar01Prefetch = 0x00, \ - .NtbXlinkCtlOverride = 0x03, \ - } - -/* - * Standard Tioga Pass Iio PCIe Port Table - */ -static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = { - CFG_UPD_PORT(PORT_1A, NOT_HIDE), - CFG_UPD_PORT(PORT_1B, HIDE), - CFG_UPD_PORT(PORT_1C, HIDE), - CFG_UPD_PORT(PORT_1D, HIDE), - CFG_UPD_PORT(PORT_2A, NOT_HIDE), - CFG_UPD_PORT(PORT_2B, HIDE), - CFG_UPD_PORT(PORT_2C, HIDE), - CFG_UPD_PORT(PORT_2D, HIDE), - CFG_UPD_PORT(PORT_3A, NOT_HIDE), - CFG_UPD_PORT(PORT_3B, HIDE), - CFG_UPD_PORT(PORT_3C, NOT_HIDE), - CFG_UPD_PORT(PORT_3D, HIDE), -}; - -/* - * Standard Tioga Pass PCH PCIe Port Table - */ -static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = { - //PortIndex ; ForceEnable ; PortLinkSpeed - { 0x00, 0x00, PcieAuto }, - { 0x04, 0x00, PcieAuto }, - { 0x05, 0x00, PcieAuto }, -}; - -#endif /* _SKXSP_TP_IIO_H_ */ diff --git a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h deleted file mode 100644 index 59ab3e7..0000000 --- a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h +++ /dev/null @@ -1,543 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CFG_PCH_GPIO_H -#define CFG_PCH_GPIO_H - -#include <soc/gpio.h> - -/* Pad configuration table for C621 Lewisburg PCH */ -static const struct pad_config gpio_table[] = { - /* ------- GPIO Community 0 ------- */ - /* ------- GPIO Group GPP_A ------- */ - /* GPP_A0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A0, NONE, DEEP, OFF, DRIVER), - /* GPP_A1 - LAD0 */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - /* GPP_A2 - LAD1 */ - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - /* GPP_A3 - LAD2 */ - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - /* GPP_A4 - LAD3 */ - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - /* GPP_A5 - LFRAME# */ - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - /* GPP_A6 - SERIRQ */ - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - /* GPP_A7 - PIRQA# */ - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), - /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - /* GPP_A10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, DEEP, OFF, DRIVER), - /* GPP_A11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), - /* GPP_A12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, DRIVER), - /* GPP_A13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, DEEP, OFF, DRIVER), - /* GPP_A14 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, DEEP, OFF, DRIVER), - /* GPP_A15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), - /* GPP_A16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A16, NONE, DEEP, OFF, DRIVER), - /* GPP_A17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, DEEP, OFF, DRIVER), - /* GPP_A18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, DRIVER), - /* GPP_A19 - RESERVED */ - /* GPP_A20 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, DRIVER), - /* GPP_A21 - GPIO */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), - /* GPP_A22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, DRIVER), - /* GPP_A23 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Group GPP_B ------- */ - /* GPP_B0 - CORE_VID0 */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), - /* GPP_B1 - CORE_VID1 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - /* GPP_B2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, DRIVER), - /* GPP_B3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, DRIVER), - /* GPP_B4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, DRIVER), - /* GPP_B5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, DEEP, OFF, DRIVER), - /* GPP_B6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, DRIVER), - /* GPP_B7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, DRIVER), - /* GPP_B8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, DEEP, OFF, DRIVER), - /* GPP_B9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, DEEP, OFF, DRIVER), - /* GPP_B10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, DRIVER), - /* GPP_B11 - GPIO */ - PAD_CFG_GPO(GPP_B11, 1, DEEP), - /* GPP_B12 - GLB_RST_WARN_N# */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - /* GPP_B13 - PLTRST# */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* GPP_B14 - SPKR */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), - /* GPP_B15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, DRIVER), - /* GPP_B16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, DEEP, OFF, DRIVER), - /* GPP_B17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, DEEP, OFF, DRIVER), - /* GPP_B18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, DEEP, OFF, DRIVER), - /* GPP_B19 - GPIO */ - PAD_CFG_GPO(GPP_B19, 1, DEEP), - /* GPP_B20 - GPIO */ - PAD_CFG_GPO(GPP_B20, 1, DEEP), - /* GPP_B21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, DRIVER), - /* GPP_B22 - GPIO */ - PAD_CFG_GPO(GPP_B22, 0, DEEP), - /* GPP_B23 - PCHHOT# */ - PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2), - - /* ------- GPIO Group GPP_F ------- */ - /* GPP_F0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, DEEP, OFF, DRIVER), - /* GPP_F1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, DRIVER), - /* GPP_F2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, DRIVER), - /* GPP_F3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, DRIVER), - /* GPP_F4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, DRIVER), - /* GPP_F5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, DEEP, OFF, DRIVER), - /* GPP_F6 - GPIO */ - PAD_CFG_GPO(GPP_F6, 0, PLTRST), - /* GPP_F7 - GPIO */ - PAD_CFG_GPO(GPP_F7, 0, PLTRST), - /* GPP_F8 - GPIO */ - PAD_CFG_GPO(GPP_F8, 0, PLTRST), - /* GPP_F9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), - /* GPP_F10 - SATA_SCLOCK */ - PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), - /* GPP_F11 - SATA_SLOAD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* GPP_F12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, DRIVER), - /* GPP_F13 - SATA_SDATAOUT2 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* GPP_F14 - SSATA_LED# */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF3), - /* GPP_F15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, DRIVER), - /* GPP_F16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, DRIVER), - /* GPP_F17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, DEEP, OFF, DRIVER), - /* GPP_F18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, DEEP, OFF, DRIVER), - /* GPP_F19 - LAN_SMBCLK */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* GPP_F20 - LAN_SMBDATA */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* GPP_F21 - LAN_SMBALRT# */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* GPP_F22 - SSATA_SCLOCK */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), - /* GPP_F23 - SSATA_SLOAD */ - PAD_CFG_NF(GPP_F23, NONE, DEEP, NF3), - - /* ------- GPIO Community 1 ------- */ - /* ------- GPIO Group GPP_C ------- */ - /* GPP_C0 - RESERVED */ - /* GPP_C1 - RESERVED */ - /* GPP_C2 - SMBALERT# */ - PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), - /* GPP_C3 - RESERVED */ - /* GPP_C4 - RESERVED */ - /* GPP_C5 - GPIO */ - PAD_CFG_GPO(GPP_C5, 0, DEEP), - /* GPP_C6 - RESERVED */ - /* GPP_C7 - RESERVED */ - /* GPP_C8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, DEEP, OFF, DRIVER), - /* GPP_C9 - GPIO */ - PAD_CFG_GPO(GPP_C9, 1, DEEP), - /* GPP_C10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, EDGE_BOTH, ACPI), - /* GPP_C11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, DEEP, OFF, DRIVER), - /* GPP_C12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, DEEP, OFF, DRIVER), - /* GPP_C13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, DEEP, OFF, DRIVER), - /* GPP_C14 - GPIO */ - PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), - /* GPP_C15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, DRIVER), - /* GPP_C16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, DEEP, OFF, DRIVER), - /* GPP_C17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, DEEP, OFF, DRIVER), - /* GPP_C18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, DEEP, OFF, DRIVER), - /* GPP_C19 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, DEEP, OFF, DRIVER), - /* GPP_C20 - RESERVED */ - /* GPP_C21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, DEEP, OFF, DRIVER), - /* GPP_C22 - GPIO */ - PAD_CFG_GPI_SMI(GPP_C22, NONE, PLTRST, LEVEL, NONE), - /* GPP_C23 - GPIO */ - PAD_CFG_GPI_SMI(GPP_C23, NONE, DEEP, LEVEL, INVERT), - - /* ------- GPIO Group GPP_D ------- */ - /* GPP_D0 - GPIO */ - PAD_CFG_GPI_SMI(GPP_D0, NONE, PLTRST, LEVEL, INVERT), - /* GPP_D1 - GPIO */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* GPP_D2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, DRIVER), - /* GPP_D3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, DRIVER), - /* GPP_D4 - GPIO */ - PAD_CFG_GPO(GPP_D4, 1, DEEP), - /* GPP_D5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, DRIVER), - /* GPP_D6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, DRIVER), - /* GPP_D7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, DRIVER), - /* GPP_D8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, DEEP, OFF, DRIVER), - /* GPP_D9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, OFF, DRIVER), - /* GPP_D10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, DRIVER), - /* GPP_D11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, OFF, DRIVER), - /* GPP_D12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, OFF, DRIVER), - /* GPP_D13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, DRIVER), - /* GPP_D14 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, DRIVER), - /* GPP_D15 - SSATA_SDATAOUT0 */ - PAD_CFG_NF(GPP_D15, NONE, DEEP, NF3), - /* GPP_D16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, DRIVER), - /* GPP_D17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, DRIVER), - /* GPP_D18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, DRIVER), - /* GPP_D19 - GPIO */ - PAD_CFG_GPO(GPP_D19, 1, DEEP), - /* GPP_D20 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, DEEP, OFF, DRIVER), - /* GPP_D21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, DEEP, OFF, DRIVER), - /* GPP_D22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, DRIVER), - /* GPP_D23 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Group GPP_E ------- */ - /* GPP_E0 - GPIO */ - PAD_CFG_GPI_SMI(GPP_E0, NONE, DEEP, LEVEL, NONE), - /* GPP_E1 - GPIO */ - PAD_CFG_GPI_SMI(GPP_E1, NONE, DEEP, LEVEL, NONE), - /* GPP_E2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER), - /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), - /* GPP_E4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, DRIVER), - /* GPP_E5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, DRIVER), - /* GPP_E6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, DRIVER), - /* GPP_E7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, DRIVER), - /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* GPP_E10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, DRIVER), - /* GPP_E11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, DRIVER), - /* GPP_E12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Community 2 ------- */ - /* -------- GPIO Group GPD -------- */ - /* GPD0 - RESERVED */ - /* GPD1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, RSMRST, OFF, ACPI), - /* GPD2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, RSMRST, OFF, ACPI), - /* GPD3 - PWRBTN# */ - PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), - /* GPD4 - SLP_S3# */ - PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), - /* GPD5 - SLP_S4# */ - PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), - /* GPD6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), - /* GPD7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI), - /* GPD8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), - /* GPD9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), - /* GPD10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, RSMRST, OFF, ACPI), - /* GPD11 - GBEPHY */ - PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), - - /* ------- GPIO Community 3 ------- */ - /* ------- GPIO Group GPP_I ------- */ - /* GPP_I0 - LAN_TDO */ - PAD_CFG_NF(GPP_I0, NONE, DEEP, NF2), - /* GPP_I1 - LAN_TCK */ - PAD_CFG_NF(GPP_I1, NONE, DEEP, NF2), - /* GPP_I2 - LAN_TMS */ - PAD_CFG_NF(GPP_I2, NONE, DEEP, NF2), - /* GPP_I3 - LAN_TDI */ - PAD_CFG_NF(GPP_I3, NONE, DEEP, NF2), - /* GPP_I4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, DRIVER), - /* GPP_I5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, DEEP, OFF, DRIVER), - /* GPP_I6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, DRIVER), - /* GPP_I7 - LAN_TRST_IN */ - PAD_CFG_NF(GPP_I7, NONE, DEEP, NF2), - /* GPP_I8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, DRIVER), - /* GPP_I9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, DEEP, OFF, DRIVER), - /* GPP_I10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Community 4 ------- */ - /* ------- GPIO Group GPP_J ------- */ - /* GPP_J0 - LAN_LED_P0_0 */ - PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), - /* GPP_J1 - LAN_LED_P0_1 */ - PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), - /* GPP_J2 - LAN_LED_P1_0 */ - PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), - /* GPP_J3 - LAN_LED_P1_1 */ - PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), - /* GPP_J4 - LAN_LED_P2_0 */ - PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), - /* GPP_J5 - LAN_LED_P2_1 */ - PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), - /* GPP_J6 - LAN_LED_P3_0 */ - PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), - /* GPP_J7 - LAN_LED_P3_1 */ - PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), - /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ - PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), - /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ - PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), - /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ - PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), - /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ - PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), - /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ - PAD_CFG_NF(GPP_J12, NONE, DEEP, NF1), - /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ - PAD_CFG_NF(GPP_J13, NONE, DEEP, NF1), - /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ - PAD_CFG_NF(GPP_J14, NONE, DEEP, NF1), - /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ - PAD_CFG_NF(GPP_J15, NONE, DEEP, NF1), - /* GPP_J16 - LAN_SDP_P0_0 */ - PAD_CFG_NF(GPP_J16, NONE, DEEP, NF1), - /* GPP_J17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, DEEP, OFF, DRIVER), - /* GPP_J18 - LAN_SDP_P1_0 */ - PAD_CFG_NF(GPP_J18, NONE, DEEP, NF1), - /* GPP_J19 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, DEEP, OFF, DRIVER), - /* GPP_J20 - LAN_SDP_P2_0 */ - PAD_CFG_NF(GPP_J20, NONE, DEEP, NF1), - /* GPP_J21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, DEEP, OFF, DRIVER), - /* GPP_J22 - LAN_SDP_P3_0 */ - PAD_CFG_NF(GPP_J22, NONE, DEEP, NF1), - /* GPP_J23 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Group GPP_K ------- */ - /* GPP_K0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, DEEP, OFF, DRIVER), - /* GPP_K1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, DEEP, OFF, DRIVER), - /* GPP_K2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, DEEP, OFF, DRIVER), - /* GPP_K3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, DEEP, OFF, DRIVER), - /* GPP_K4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, DEEP, OFF, DRIVER), - /* GPP_K5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, DEEP, OFF, DRIVER), - /* GPP_K6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, DRIVER), - /* GPP_K7 - RESERVED */ - PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), - /* GPP_K8 - LAN_NCSI_ARB_IN */ - PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), - /* GPP_K9 - LAN_NCSI_ARB_OUT */ - PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), - /* GPP_K10 - PE_RST# */ - PAD_CFG_NF(GPP_K10, NONE, DEEP, NF1), - - /* ------- GPIO Community 5 ------- */ - /* ------- GPIO Group GPP_G ------- */ - /* GPP_G0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, DRIVER), - /* GPP_G1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, DRIVER), - /* GPP_G2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, DRIVER), - /* GPP_G3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, DRIVER), - /* GPP_G4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, DEEP, OFF, DRIVER), - /* GPP_G5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, DEEP, OFF, DRIVER), - /* GPP_G6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, DEEP, OFF, DRIVER), - /* GPP_G7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, DRIVER), - /* GPP_G8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, DEEP, OFF, DRIVER), - /* GPP_G9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, DEEP, OFF, DRIVER), - /* GPP_G10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, DRIVER), - /* GPP_G11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, DRIVER), - /* GPP_G12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, DEEP, OFF, DRIVER), - /* GPP_G13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, DRIVER), - /* GPP_G14 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, DEEP, OFF, DRIVER), - /* GPP_G15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, DEEP, OFF, DRIVER), - /* GPP_G16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, DEEP, OFF, DRIVER), - /* GPP_G17 - ADR_COMPLETE */ - PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), - /* GPP_G18 - NMI# */ - PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), - /* GPP_G19 - SMI# */ - PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), - /* GPP_G20 - RESERVED */ - /* GPP_G21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, DEEP, OFF, DRIVER), - /* GPP_G22 - GPIO */ - PAD_CFG_GPO(GPP_G22, 1, DEEP), - /* GPP_G23 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Group GPP_H ------- */ - /* GPP_H0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, DEEP, OFF, DRIVER), - /* GPP_H1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, DEEP, OFF, DRIVER), - /* GPP_H2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, DEEP, OFF, DRIVER), - /* GPP_H3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, DRIVER), - /* GPP_H4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, DEEP, OFF, DRIVER), - /* GPP_H5 - RESERVED */ - /* GPP_H6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, DEEP, OFF, DRIVER), - /* GPP_H7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, DEEP, OFF, DRIVER), - /* GPP_H8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, DEEP, OFF, DRIVER), - /* GPP_H9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, DEEP, OFF, DRIVER), - /* GPP_H10 - RESERVED */ - /* GPP_H11 - RESERVED */ - /* GPP_H12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, DEEP, OFF, DRIVER), - /* GPP_H13 - RESERVED */ - /* GPP_H14 - RESERVED */ - /* GPP_H15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, DRIVER), - /* GPP_H16 - RESERVED */ - /* GPP_H17 - RESERVED */ - /* GPP_H18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, DEEP, OFF, DRIVER), - /* GPP_H19 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, DRIVER), - /* GPP_H20 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, DEEP, OFF, DRIVER), - /* GPP_H21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, DEEP, OFF, DRIVER), - /* GPP_H22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, DEEP, OFF, DRIVER), - /* GPP_H23 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Group GPP_L ------- */ - /* GPP_L0 - RESERVED */ - /* GPP_L1 - CSME_INTR_OUT */ - PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1), - /* GPP_L2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, DRIVER), - /* GPP_L3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, DRIVER), - /* GPP_L4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, DRIVER), - /* GPP_L5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, DRIVER), - /* GPP_L6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, DRIVER), - /* GPP_L7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, DEEP, OFF, DRIVER), - /* GPP_L8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L8, NONE, DEEP, OFF, DRIVER), - /* GPP_L9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L9, NONE, DEEP, OFF, DRIVER), - /* GPP_L10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L10, NONE, DEEP, OFF, DRIVER), - /* GPP_L11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L11, NONE, DEEP, OFF, DRIVER), - /* GPP_L12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L12, NONE, DEEP, OFF, DRIVER), - /* GPP_L13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L13, NONE, DEEP, OFF, DRIVER), - /* GPP_L14 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L14, NONE, DEEP, OFF, DRIVER), - /* GPP_L15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L15, NONE, DEEP, OFF, DRIVER), - /* GPP_L16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L16, NONE, DEEP, OFF, DRIVER), - /* GPP_L17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L17, NONE, DEEP, OFF, DRIVER), - /* GPP_L18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L18, NONE, DEEP, OFF, DRIVER), - /* GPP_L19 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L19, NONE, DEEP, OFF, DRIVER), -}; - -#endif /* CFG_PCH_GPIO_H */ diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c deleted file mode 100644 index e97341b..0000000 --- a/src/mainboard/ocp/tiogapass/ipmi.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <drivers/ipmi/ipmi_if.h> -#include <drivers/ipmi/ipmi_ops.h> -#include <drivers/ipmi/ocp/ipmi_ocp.h> -#include <drivers/vpd/vpd.h> -#include <string.h> - -#include "ipmi.h" -#include "vpd.h" - -void init_frb2_wdt(void) -{ - char val[VPD_LEN]; - /* Enable FRB2 timer by default. */ - u8 enable = 1; - uint16_t countdown; - - if (vpd_get_bool(FRB2_TIMER, VPD_RW_THEN_RO, &enable)) { - if (!enable) { - printk(BIOS_DEBUG, "Disable FRB2 timer\n"); - ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE); - return; - } - } - if (enable) { - if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW_THEN_RO)) { - countdown = (uint16_t)atol(val); - printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d ms\n", - countdown * 100); - } else { - printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n", - DEFAULT_COUNTDOWN * 100); - countdown = DEFAULT_COUNTDOWN; - } - ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, countdown, - TIMEOUT_HARD_RESET); - } -} diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h deleted file mode 100644 index 93101c2..0000000 --- a/src/mainboard/ocp/tiogapass/ipmi.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef TIOGAPASS_IPMI_H -#define TIOGAPASS_IPMI_H -#include <types.h> - -void init_frb2_wdt(void); -#endif diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c deleted file mode 100644 index c69322b..0000000 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ /dev/null @@ -1,182 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <drivers/ipmi/ipmi_ops.h> -#include <drivers/ocp/dmi/ocp_dmi.h> -#include <soc/ramstage.h> - -extern struct fru_info_str fru_strings; - -static const struct port_information SMBIOS_type8_info[] = { - /* - * Port Information fields: - * Internal Reference Designator, - * Internal Connector Type, - * External Reference Designator, - * External Connector_Type, - * Port Type - */ - { - "J7F5 - BMC JTAG HEADER", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - "J8A1 - MINISAS1", - CONN_SAS_SATA, - NULL, - CONN_NONE, - TYPE_SAS - }, - { - "J8A2 - MINISAS2", - CONN_SAS_SATA, - NULL, - CONN_NONE, - TYPE_SAS - }, - { - "J8A3 - SATA CONBINE1", - CONN_SAS_SATA, - NULL, - CONN_NONE, - TYPE_SAS - }, - { - "J8B1 - ME_DBG", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - "J8D1 - VR_DBG", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - "J8E1 - TPM_MODULE", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - "J8F1 - M.2 CONNECTOR", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - "J9A1 - SATA RAID KEY", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - NULL, - CONN_NONE, - "J9A2 - DEBUG 80 PORT", - CONN_OTHER, - TYPE_OTHER_PORT - }, - { - "J9A3 - CPU & PCH XDP", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - NULL, - CONN_NONE, - "J9A5 - USB conn", - CONN_ACCESS_BUS_USB, - TYPE_USB - }, - { - "J9B1 - BMC_DBG", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - NULL, - CONN_NONE, - "J9D1 - USB3.0 TYPE C", - CONN_ACCESS_BUS_USB, - TYPE_USB - }, - { - NULL, - CONN_NONE, - "J9E1 - VGA", - CONN_OTHER, - TYPE_OTHER_PORT - }, - { - NULL, - CONN_NONE, - "JA9G1 - ETH0", - CONN_RJ_45, - TYPE_NETWORK_PORT - }, -}; - -void mainboard_silicon_init_params(FSPS_UPD *params) -{ -} - -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) -{ - int len = 0; - - // add port information - len += smbios_write_type8( - current, handle, - SMBIOS_type8_info, - ARRAY_SIZE(SMBIOS_type8_info) - ); - - return len; -} -#endif - -static void tp_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) -{ - /* OEM string 1 to 6 */ - ocp_oem_smbios_strings(dev, t); - - /* OEM string 7 */ - if (fru_strings.board_info.custom_count > 1 && - *(fru_strings.board_info.board_custom + 1) != NULL) - t->count = smbios_add_oem_string(t->eos, - *(fru_strings.board_info.board_custom + 1)); - else - t->count = smbios_add_oem_string(t->eos, TBF); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->get_smbios_strings = tp_oem_smbios_strings; - read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings); -#if CONFIG(GENERATE_SMBIOS_TABLES) - dev->ops->get_smbios_data = mainboard_smbios_data; -#endif -} - -static void mainboard_final(void *chip_info) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - .final = mainboard_final, -}; diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c deleted file mode 100644 index d3063c6..0000000 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <fsp/api.h> -#include <FspmUpd.h> -#include <drivers/ipmi/ipmi_if.h> -#include <drivers/ipmi/ocp/ipmi_ocp.h> -#include <soc/romstage.h> -#include <string.h> -#include <gpio.h> -#include <soc/gpio_soc_defs.h> -#include <skxsp_tp_iio.h> - -#include "ipmi.h" - -static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; - -static void oem_update_iio(FSPM_UPD *mupd) -{ - /* Read GPIO to decide IIO bifurcation at run-time. */ - int slot_config0 = gpio_get(GPP_C15); - int slot_config1 = gpio_get(GPP_C16); - - /* It's a single side 3 slots riser card, to tell which AICs are on each slot requires - reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation - accordingly is left for future work. */ - if (!slot_config0 && slot_config1) - mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation - = IIO_BIFURCATE_xxx8xxx8; -} - -static void mainboard_config_iio(FSPM_UPD *mupd) -{ - memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); - mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = - (UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf; - mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = - ARRAY_SIZE(tp_iio_bifur_table); - - mupd->FspmConfig.IioPciConfig.ConfigurationTable = - (UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0; - mupd->FspmConfig.IioPciConfig.NumberOfEntries = - ARRAY_SIZE(tp_iio_pci_port_skt0); - - mupd->FspmConfig.PchPciConfig.PciPortConfig = - (UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0; - mupd->FspmConfig.PchPciConfig.NumberOfEntries = - ARRAY_SIZE(tp_pch_pci_port_skt0); - - mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00; - mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00; - oem_update_iio(mupd); -} - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - /* It's better to run get BMC selftest result first */ - if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { - ipmi_set_post_start(CONFIG_BMC_KCS_BASE); - init_frb2_wdt(); - } - mainboard_config_iio(mupd); - - /* do not configure GPIO controller inside FSP-M */ - mupd->FspmConfig.GpioConfig.GpioTable = NULL; - mupd->FspmConfig.GpioConfig.NumberOfEntries = 0; -} diff --git a/src/mainboard/ocp/tiogapass/vpd.h b/src/mainboard/ocp/tiogapass/vpd.h deleted file mode 100644 index 63a92f6..0000000 --- a/src/mainboard/ocp/tiogapass/vpd.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef TIOGAPASS_VPD_H -#define TIOGAPASS_VPD_H - -/* VPD variable for enabling/disabling FRB2 timer. */ -#define FRB2_TIMER "frb2_timer" -/* VPD variable for setting FRB2 timer countdown value. */ -#define FRB2_COUNTDOWN "frb2_countdown" -#define VPD_LEN 10 -/* Default countdown is 15 minutes. */ -#define DEFAULT_COUNTDOWN 9000 - -#endif /* TIOGAPASS_VPD_H */