Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81924?usp=email )
Change subject: sb/intel/bd82x6x/pch.asl: Remove GPIO configuration access ......................................................................
sb/intel/bd82x6x/pch.asl: Remove GPIO configuration access
Allowing access to change GPIO configuration from ACPI is asking for trouble. Kill it while nobody cares (yet).
Access to mainpulate and blink GPIOs is maintained.
Change-Id: Id80a7e2f815a58750623c133bb30e5ed84a6e2ed Signed-off-by: Keith Hui buurin@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/81924 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/southbridge/intel/bd82x6x/acpi/pch.asl 1 file changed, 0 insertions(+), 25 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 5d74261..5ecbbd5 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -54,15 +54,6 @@ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) Field(GPIO, ByteAcc, NoLock, Preserve) { - GU00, 8, // GPIO Use Select - GU01, 8, - GU02, 8, - GU03, 8, - Offset(0x04), // GPIO IO Select - GIO0, 8, - GIO1, 8, - GIO2, 8, - GIO3, 8, Offset(0x0c), // GPIO Level GP00, 1, GP01, 1, @@ -134,16 +125,6 @@ GIV1, 8, GIV2, 8, GIV3, 8, - Offset(0x30), // GPIO Use Select 2 - GU04, 8, - GU05, 8, - GU06, 8, - GU07, 8, - Offset(0x34), // GPIO IO Select 2 - GIO4, 8, - GIO5, 8, - GIO6, 8, - GIO7, 8, Offset(0x38), // GPIO Level 2 GP32, 1, GP33, 1, @@ -177,12 +158,6 @@ GP61, 1, GP62, 1, GP63, 1, - Offset(0x40), // GPIO Use Select 3 - GU08, 8, - GU09, 4, - Offset(0x44), // GPIO IO Select 3 - GIO8, 8, - GIO9, 4, Offset(0x48), // GPIO Level 3 GP64, 1, GP65, 1,