Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 )
Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ......................................................................
Patch Set 7:
(5 comments)
https://review.coreboot.org/c/coreboot/+/46842/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46842/6//COMMIT_MSG@27 PS6, Line 27: Correcting the sequence by moving some of the reserved gpio within : community (that's also same in pinctrl driver), helps with the issue.
What you are really doing is creating pad groups as per the EDS. […]
Yes Furquan. I have updated comment and also provided ref to EDS.
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... File src/soc/intel/jasperlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... PS6, Line 36: 0
This is not correct. It should be 320: https://source.chromium. […]
Ack
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... PS6, Line 37: INTEL_GPP(GPP_F0, GPIO_RSVD_0, GPIO_RSVD_8),
BTW, I think the kernel has a bug: https://source.chromium. […]
Ack Sure Furquan. Let me check with this in kernel and also follow up internally.
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... PS6, Line 38: GPIO_RSVD_10
Not for this change, but I think this GPIO should be named as per EDS. […]
Ack
https://review.coreboot.org/c/coreboot/+/46842/6/src/soc/intel/jasperlake/gp... PS6, Line 39: GPIO_RSVD_11
Same here and the other GPIO_RSVD* below.
Ack