[coreboot-gerrit] [S] Change in coreboot[master]: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz

[Rex-BC Chen (Code Review)]

Attention is currently required from: Hung-Te Lin, Bayi Cheng, Yu-Ping Wu, Yidi Lin.

Hello Hung-Te Lin, Bayi Cheng, Yu-Ping Wu, Yidi Lin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/68659

to look at the new patch set (#2).

Change subject: soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz
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soc/mediatek/mt8186: Lower SPI NOR frequency from 52Mhz to 39Mhz

According to the datasheet, the maximum frequency supported by
{winbond SPI model} is 50Mhz. To meet this restriction, we lower the
NOR clock from 52Mhz to 39 Mhz which is the closest frequency of the
next clock level on MT8186.

We change the NOR flash clcok parent and adjust the clock from 52M to
39M which is the next lower level of clock for MT8186 NOR.

BUG=b:253167106
TEST=emerge-corsola coreboot.
TEST=Boot time didn't increase significantly.
BRAHCH=corsola

Signed-off-by: Dandan He 
Signed-off-by: Bayi Cheng 
Change-Id: Ibcf4549fefa28b2ad9c38e31ec9a69f8afeff3fd
---
M src/soc/mediatek/mt8186/pll.c
1 file changed, 25 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/68659/2