Nicolas Reinecke (nr@das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7100
-gerrit
commit 7788ee393139dc94bf6fd44ef82de7c1dd55baea Author: Nicolas Reinecke nr@das-labor.org Date: Fri Oct 17 13:01:02 2014 +0200
lenovo/t520: Use native LVDS gfx init
As introduced in: 1783a3c ivybridge: LVDS gfx init.
The panel on the T520 is a LP156WD1 40 pin LVDS (2 ch, 6-bit). Tx parameters derived from datasheet table.
Change-Id: Ib733836e3233a7f14a79f36a27ed36b638e837f5 Signed-off-by: Nicolas Reinecke nr@das-labor.org --- src/mainboard/lenovo/t520/Kconfig | 6 ++++++ src/mainboard/lenovo/t520/devicetree.cb | 16 +++++++++++----- 2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index f204158..763cd17 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -15,6 +15,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select INTEL_INT15 + select EARLY_CBMEM_INIT + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select SANDYBRIDGE_LVDS
# Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index c911d99..c32e237 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -5,11 +5,17 @@ chip northbridge/intel/sandybridge
# Enable Panel as LVDS and configure power delays register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms - register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms - register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms + register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms + register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x06100610"
device cpu_cluster 0 on chip cpu/intel/socket_rPGA988B